linux-kernel - Re: [RFC/PATCH 1/1] tools headers arm64: Sync arm64's cputype.h with the kernel sources

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Message-ID: <Zl8cYk0Tai2fs7aM@x1>
Date: Tue, 4 Jun 2024 10:53:38 -0300
From: Arnaldo Carvalho de Melo <acme@...nel.org>
To: Mark Rutland <mark.rutland@....com>
Cc: Besar Wicaksono <bwicaksono@...dia.com>, Will Deacon <will@...nel.org>,
	Adrian Hunter <adrian.hunter@...el.com>,
	Ian Rogers <irogers@...gle.com>, Jiri Olsa <jolsa@...nel.org>,
	Kan Liang <kan.liang@...ux.intel.com>,
	Namhyung Kim <namhyung@...nel.org>,
	Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
	linux-perf-users@...r.kernel.org
Subject: Re: [RFC/PATCH 1/1] tools headers arm64: Sync arm64's cputype.h with
 the kernel sources

On Tue, Jun 04, 2024 at 10:11:22AM +0100, Mark Rutland wrote:
> Hi Arnaldo,
> 
> On Mon, Jun 03, 2024 at 03:33:07PM -0300, Arnaldo Carvalho de Melo wrote:
> > To get the changes in:
> > 
> >   0ce85db6c2141b7f ("arm64: cputype: Add Neoverse-V3 definitions")
> >   02a0a04676fa7796 ("arm64: cputype: Add Cortex-X4 definitions")
> >   f4d9d9dcc70b96b5 ("arm64: Add Neoverse-V2 part")
> 
> As a heads-up, there are likely to be a couple more updates here
> shortly:
> 
>   https://lore.kernel.org/linux-arm-kernel/20240603111812.1514101-1-mark.rutland@arm.com/
> 
> > That makes this perf source code to be rebuilt:
> > 
> >   CC      /tmp/build/perf-tools/util/arm-spe.o
> > 
> > The changes in the above patch add MIDR_NEOVERSE_V[23] and
> > MIDR_NEOVERSE_V1 is used in arm-spe.c, so probably we need to add those
> > and perhaps MIDR_CORTEX_X4 to that array? Or maybe we need to leave this
> > for later when this is all tested on those machines?
> 
> Hmm... looking at where that was added this is somewhat misnamed, this
> is really saying that these cores use the same IMPLEMENTATION DEFINED
> encoding of the source field. That's not really a property of Neoverse
> specifically, and I'm not sure what Arm's policy is here going forwards.
> 
> We should probably rename that to something like
> common_data_source_encoding, with a big comment about exactly what it
> implies.
> 
> I would not touch this for now -- someone would have to go audit the

Ok, you mean not touch tools/perf/util/arm-spe.c, right, can I just go
ahead and update the copy of that header so that we have a clean (of
build warnings) build?

Thanks for checking!

- Arnaldo

> TRMs to check that those other cores have the same encoding, and I think
> it'd be better to do that as a follow-up.
> 
> The relevant commit was:
> 
>   4e6430cbb1a9f1dc ("perf arm-spe: Use SPE data source for neoverse cores")
> 
> Mark.
> 
> >   static const struct midr_range neoverse_spe[] = {
> >           MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1),
> >           MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
> >           MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1),
> >           {},
> >   };
> > 
> > That addresses this perf build warning:
> > 
> >   Warning: Kernel ABI header differences:
> >     diff -u tools/arch/arm64/include/asm/cputype.h arch/arm64/include/asm/cputype.h
> > 
> > Cc: Adrian Hunter <adrian.hunter@...el.com>
> > Cc: Besar Wicaksono <bwicaksono@...dia.com>
> > Cc: Ian Rogers <irogers@...gle.com>
> > Cc: Jiri Olsa <jolsa@...nel.org>
> > Cc: Kan Liang <kan.liang@...ux.intel.com>
> > Cc: Mark Rutland <mark.rutland@....com>
> > Cc: Namhyung Kim <namhyung@...nel.org>
> > Cc: Will Deacon <will@...nel.org>
> > Link: https://lore.kernel.org/lkml/
> > Signed-off-by: Arnaldo Carvalho de Melo <acme@...hat.com>
> > ---
> >  tools/arch/arm64/include/asm/cputype.h | 6 ++++++
> >  1 file changed, 6 insertions(+)
> > 
> > diff --git a/tools/arch/arm64/include/asm/cputype.h b/tools/arch/arm64/include/asm/cputype.h
> > index 52f076afeb96006c..7b32b99023a21d3a 100644
> > --- a/tools/arch/arm64/include/asm/cputype.h
> > +++ b/tools/arch/arm64/include/asm/cputype.h
> > @@ -86,6 +86,9 @@
> >  #define ARM_CPU_PART_CORTEX_X2		0xD48
> >  #define ARM_CPU_PART_NEOVERSE_N2	0xD49
> >  #define ARM_CPU_PART_CORTEX_A78C	0xD4B
> > +#define ARM_CPU_PART_NEOVERSE_V2	0xD4F
> > +#define ARM_CPU_PART_CORTEX_X4		0xD82
> > +#define ARM_CPU_PART_NEOVERSE_V3	0xD84
> >  
> >  #define APM_CPU_PART_XGENE		0x000
> >  #define APM_CPU_VAR_POTENZA		0x00
> > @@ -159,6 +162,9 @@
> >  #define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2)
> >  #define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2)
> >  #define MIDR_CORTEX_A78C	MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78C)
> > +#define MIDR_NEOVERSE_V2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V2)
> > +#define MIDR_CORTEX_X4 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X4)
> > +#define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3)
> >  #define MIDR_THUNDERX	MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
> >  #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
> >  #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)
> > -- 
> > 2.44.0
> >