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Message-ID: <1jed95p0kq.fsf@starbuckisacylon.baylibre.com>
Date: Mon, 10 Jun 2024 12:13:41 +0200
From: Jerome Brunet <jbrunet@...libre.com>
To: Dmitry Rokosov <ddrokosov@...utedevices.com>
Cc: <neil.armstrong@...aro.org>,  <mturquette@...libre.com>,
  <sboyd@...nel.org>,  <robh+dt@...nel.org>,
  <krzysztof.kozlowski+dt@...aro.org>,  <khilman@...libre.com>,
  <martin.blumenstingl@...glemail.com>,  <jian.hu@...ogic.com>,
  <kernel@...rdevices.ru>,  <rockosov@...il.com>,
  <linux-amlogic@...ts.infradead.org>,  <linux-clk@...r.kernel.org>,
  <devicetree@...r.kernel.org>,  <linux-kernel@...r.kernel.org>,
  <linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH v3 0/7] clk: meson: introduce Amlogic A1 SoC Family CPU
 clock controller driver

On Wed 15 May 2024 at 21:47, Dmitry Rokosov <ddrokosov@...utedevices.com> wrote:

> The CPU clock controller plays a general role in the Amlogic A1 SoC
> family by generating CPU clocks. As an APB slave module, it offers the
> capability to inherit the CPU clock from two sources: the internal fixed
> clock known as 'cpu fixed clock' and the external input provided by the
> A1 PLL clock controller, referred to as 'syspll'.
>
> It is important for the driver to handle the cpu_clk rate switching
> effectively by transitioning to the CPU fixed clock to avoid any
> potential execution freezes.
>

Please group your changes, fixes then bindings then driver.

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