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Message-ID: <ce213573a9f0832c0946ea4bd5595de2b4ce73af.camel@intel.com>
Date: Mon, 10 Jun 2024 10:31:44 +0000
From: "Huang, Kai" <kai.huang@...el.com>
To: "luto@...nel.org" <luto@...nel.org>, "seanjc@...gle.com"
	<seanjc@...gle.com>, "x86@...nel.org" <x86@...nel.org>,
	"dave.hansen@...ux.intel.com" <dave.hansen@...ux.intel.com>,
	"peterz@...radead.org" <peterz@...radead.org>, "bp@...en8.de" <bp@...en8.de>,
	"mingo@...hat.com" <mingo@...hat.com>, "tglx@...utronix.de"
	<tglx@...utronix.de>, "pbonzini@...hat.com" <pbonzini@...hat.com>
CC: "Li, Xiaoyao" <xiaoyao.li@...el.com>, "kvm@...r.kernel.org"
	<kvm@...r.kernel.org>, "Kang, Shan" <shan.kang@...el.com>,
	"jmattson@...gle.com" <jmattson@...gle.com>, "linux-kernel@...r.kernel.org"
	<linux-kernel@...r.kernel.org>, "Liu, Zhao1" <zhao1.liu@...el.com>, "Li,
 Xin3" <xin3.li@...el.com>
Subject: Re: [PATCH v8 01/10] x86/cpu: KVM: Add common defines for
 architectural memory types (PAT, MTRRs, etc.)

On Wed, 2024-06-05 at 16:19 -0700, Sean Christopherson wrote:
> Add defines for the architectural memory types that can be shoved into
> various MSRs and registers, e.g. MTRRs, PAT, VMX capabilities MSRs, EPTPs,
> etc.  While most MSRs/registers support only a subset of all memory types,
> the values themselves are architectural and identical across all users.
> 
> Leave the goofy MTRR_TYPE_* definitions as-is since they are in a uapi
> header, but add compile-time assertions to connect the dots (and sanity
> check that the msr-index.h values didn't get fat-fingered).
> 
> Keep the VMX_EPTP_MT_* defines so that it's slightly more obvious that the
> EPTP holds a single memory type in 3 of its 64 bits; those bits just
> happen to be 2:0, i.e. don't need to be shifted.
> 
> Opportunistically use X86_MEMTYPE_WB instead of an open coded '6' in
> setup_vmcs_config().
> 
> No functional change intended.
> 
> Signed-off-by: Sean Christopherson <seanjc@...gle.com>
> 

If it helps,

Acked-by: Kai Huang <kai.huang@...el.com>

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