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Message-ID: <20240610-unaltered-crazily-5b63e224d633@spud>
Date: Mon, 10 Jun 2024 17:29:23 +0100
From: Conor Dooley <conor@...nel.org>
To: Charlie Jenkins <charlie@...osinc.com>
Cc: Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
Jisheng Zhang <jszhang@...nel.org>, Chen-Yu Tsai <wens@...e.org>,
Jernej Skrabec <jernej.skrabec@...il.com>,
Samuel Holland <samuel@...lland.org>,
Jonathan Corbet <corbet@....net>, Shuah Khan <shuah@...nel.org>,
Guo Ren <guoren@...nel.org>, Evan Green <evan@...osinc.com>,
Andy Chiu <andy.chiu@...ive.com>, linux-riscv@...ts.infradead.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-sunxi@...ts.linux.dev, linux-doc@...r.kernel.org,
linux-kselftest@...r.kernel.org
Subject: Re: [PATCH 02/13] dt-bindings: thead: add a vlen register length
property
On Sun, Jun 09, 2024 at 09:45:07PM -0700, Charlie Jenkins wrote:
> Add a property analogous to the vlenb CSR so that software can detect
> the vector length of each CPU prior to it being brought online.
> Currently software has to assume that the vector length read from the
> boot CPU applies to all possible CPUs. On T-Head CPUs implementing
> pre-ratification vector, reading the th.vlenb CSR may produce an illegal
> instruction trap, so this property is required on such systems.
>
> Signed-off-by: Charlie Jenkins <charlie@...osinc.com>
> ---
> Documentation/devicetree/bindings/riscv/thead.yaml | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/riscv/thead.yaml b/Documentation/devicetree/bindings/riscv/thead.yaml
> index 301912dcd290..5e578df36ac5 100644
> --- a/Documentation/devicetree/bindings/riscv/thead.yaml
> +++ b/Documentation/devicetree/bindings/riscv/thead.yaml
> @@ -28,6 +28,13 @@ properties:
> - const: sipeed,lichee-module-4a
> - const: thead,th1520
>
> +thead,vlenb:
This needs to move back into cpus.yaml, this file documents root node
compatibles (boards and socs etc) and is not for CPUs. If you want to
restrict this to T-Head CPUs only, it must be done in cpus.yaml with
a conditional `if: not: ... then: properties: thead,vlenb: false`.
Please test your bindings.
Thanks,
Conor.
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description:
> + VLEN/8, the vector register length in bytes. This property is required in
> + systems where the vector register length is not identical on all harts, or
> + the vlenb CSR is not available.
> +
> additionalProperties: true
>
> ...
>
> --
> 2.44.0
>
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