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Message-ID: <20240612070106.2060334-1-chenhuacai@loongson.cn>
Date: Wed, 12 Jun 2024 15:01:06 +0800
From: Huacai Chen <chenhuacai@...ngson.cn>
To: Thomas Gleixner <tglx@...utronix.de>
Cc: loongarch@...ts.linux.dev,
linux-kernel@...r.kernel.org,
Xuefeng Li <lixuefeng@...ngson.cn>,
Huacai Chen <chenhuacai@...il.com>,
Jiaxun Yang <jiaxun.yang@...goat.com>,
Huacai Chen <chenhuacai@...ngson.cn>,
stable@...r.kernel.org,
Tianli Xiong <xiongtianli@...ngson.cn>
Subject: [PATCH] irqchip/loongson-liointc: Set different ISRs for different cores
In the liointc hardware, there are different ISRs for different cores.
We always use core#0's ISR before but has no problem, it is because the
interrupts are routed to core#0 by default. If we change the routing,
we should set correct ISRs for different cores.
Cc: <stable@...r.kernel.org>
Signed-off-by: Tianli Xiong <xiongtianli@...ngson.cn>
Signed-off-by: Huacai Chen <chenhuacai@...ngson.cn>
---
drivers/irqchip/irq-loongson-liointc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/irqchip/irq-loongson-liointc.c b/drivers/irqchip/irq-loongson-liointc.c
index e4b33aed1c97..7c4fe7ab4b83 100644
--- a/drivers/irqchip/irq-loongson-liointc.c
+++ b/drivers/irqchip/irq-loongson-liointc.c
@@ -28,7 +28,7 @@
#define LIOINTC_INTC_CHIP_START 0x20
-#define LIOINTC_REG_INTC_STATUS (LIOINTC_INTC_CHIP_START + 0x20)
+#define LIOINTC_REG_INTC_STATUS(core) (LIOINTC_INTC_CHIP_START + 0x20 + (core) * 8)
#define LIOINTC_REG_INTC_EN_STATUS (LIOINTC_INTC_CHIP_START + 0x04)
#define LIOINTC_REG_INTC_ENABLE (LIOINTC_INTC_CHIP_START + 0x08)
#define LIOINTC_REG_INTC_DISABLE (LIOINTC_INTC_CHIP_START + 0x0c)
@@ -217,7 +217,7 @@ static int liointc_init(phys_addr_t addr, unsigned long size, int revision,
goto out_free_priv;
for (i = 0; i < LIOINTC_NUM_CORES; i++)
- priv->core_isr[i] = base + LIOINTC_REG_INTC_STATUS;
+ priv->core_isr[i] = base + LIOINTC_REG_INTC_STATUS(i);
for (i = 0; i < LIOINTC_NUM_PARENT; i++)
priv->handler[i].parent_int_map = parent_int_map[i];
--
2.43.0
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