[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <87y16ym966.ffs@tglx>
Date: Fri, 21 Jun 2024 20:40:17 +0200
From: Thomas Gleixner <tglx@...utronix.de>
To: Huacai Chen <chenhuacai@...ngson.cn>
Cc: loongarch@...ts.linux.dev, linux-kernel@...r.kernel.org, Xuefeng Li
<lixuefeng@...ngson.cn>, Huacai Chen <chenhuacai@...il.com>, Jiaxun Yang
<jiaxun.yang@...goat.com>, Huacai Chen <chenhuacai@...ngson.cn>,
stable@...r.kernel.org, Tianli Xiong <xiongtianli@...ngson.cn>
Subject: Re: [PATCH] irqchip/loongson-liointc: Set different ISRs for
different cores
On Wed, Jun 12 2024 at 15:01, Huacai Chen wrote:
> In the liointc hardware, there are different ISRs for different cores.
I have no idea what ISR means in that context. Can you please spell it
out with proper words so that people not familiar with the details can
understand it?
> We always use core#0's ISR before but has no problem, it is because the
> interrupts are routed to core#0 by default. If we change the routing,
> we should set correct ISRs for different cores.
We do nothing. The code does.
See https://www.kernel.org/doc/html/latest/process/maintainer-tip.html#changelog
> Cc: <stable@...r.kernel.org>
> Signed-off-by: Tianli Xiong <xiongtianli@...ngson.cn>
> Signed-off-by: Huacai Chen <chenhuacai@...ngson.cn>
This Signed-off-by chain is wrong. If Tianli is the author then this
needs a From: Tianli in the changelog. If you developed it together then
this lacks a Co-developed-by tag.
See Documentation/process/
Thanks,
tglx
Powered by blists - more mailing lists