linux-kernel - Re: [PATCH 5/5] phy: exynos5-usbdrd: set ref clk freq in exynos850_usbdrd_utmi

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Message-ID: <CADrjBPqvdBsLVNeXVtqWp=hGS0G_=0jYQ_91pyg6jvFPN+2CvQ@mail.gmail.com>
Date: Wed, 12 Jun 2024 10:37:52 +0100
From: Peter Griffin <peter.griffin@...aro.org>
To: André Draszik <andre.draszik@...aro.org>
Cc: Vinod Koul <vkoul@...nel.org>, Kishon Vijay Abraham I <kishon@...nel.org>, 
	Krzysztof Kozlowski <krzk@...nel.org>, Alim Akhtar <alim.akhtar@...sung.com>, 
	Sam Protsenko <semen.protsenko@...aro.org>, Tudor Ambarus <tudor.ambarus@...aro.org>, 
	Will McVicker <willmcvicker@...gle.com>, kernel-team@...roid.com, 
	linux-phy@...ts.infradead.org, linux-arm-kernel@...ts.infradead.org, 
	linux-samsung-soc@...r.kernel.org, linux-kernel@...r.kernel.org, 
	Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
Subject: Re: [PATCH 5/5] phy: exynos5-usbdrd: set ref clk freq in exynos850_usbdrd_utmi_init()

Hi André,

On Tue, 7 May 2024 at 15:14, André Draszik <andre.draszik@...aro.org> wrote:
>
> While commit 255ec3879dd4 ("phy: exynos5-usbdrd: Add 26MHz ref clk
> support") correctly states that CLKRSTCTRL[7:5] doesn't need to be set
> on modern Exynos platforms, SSPPLLCTL[2:0] should be programmed with
> the frequency of the reference clock for the USB2.0 phy instead.
>
> I stumbled across this while adding support for the Google Tensor
> gs101, but this should apply to E850 just the same.
>
> Do so.
>
> Fixes: 691525074db9 ("phy: exynos5-usbdrd: Add Exynos850 support")
> Signed-off-by: André Draszik <andre.draszik@...aro.org>
>
> ---
> Feel free to drop the Fixes: if you think that is unwarranted here.
>
> v2: add missing bitfield.h include (seems this is implied on some
>     platforms, but not on others)
> ---

Reviewed-by:  Peter Griffin <peter.griffin@...aro.org>

regards,

Peter

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