linux-kernel - Re: Re : [PATCH v1] riscv: dts: starfive: add PCIe dts configuration for JH7110

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Message-ID: <20240612-italicize-cultural-a10b8a387520@spud>
Date: Wed, 12 Jun 2024 12:15:47 +0100
From: Conor Dooley <conor@...nel.org>
To: Minda Chen <minda.chen@...rfivetech.com>
Cc: Rob Herring <robh+dt@...nel.org>,
	Emil Renner Berthing <emil.renner.berthing@...onical.com>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"linux-riscv@...ts.infradead.org" <linux-riscv@...ts.infradead.org>,
	Paul Walmsley <paul.walmsley@...ive.com>,
	Palmer Dabbelt <palmer@...belt.com>,
	Albert Ou <aou@...s.berkeley.edu>
Subject: Re: Re : [PATCH v1] riscv: dts: starfive: add PCIe dts configuration
 for JH7110

On Wed, Jun 12, 2024 at 01:48:55AM +0000, Minda Chen wrote:
> 
> 
> > 
> > On Tue, Jun 11, 2024 at 09:52:00AM +0800, Minda Chen wrote:
> > > Add PCIe dts configuraion for JH7110 SoC platform.
> > >
> > > Signed-off-by: Minda Chen <minda.chen@...rfivetech.com>
> > > Reviewed-by: Hal Feng <hal.feng@...rfivetech.com>
> > > ---
> > >  .../boot/dts/starfive/jh7110-common.dtsi      | 64 ++++++++++++++
> > >  arch/riscv/boot/dts/starfive/jh7110.dtsi      | 86 +++++++++++++++++++
> > >  2 files changed, 150 insertions(+)
> > >
> > > diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
> > > b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
> > > index 8ff6ea64f048..1da7379f4e08 100644
> > > --- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
> > > +++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
> > > @@ -294,6 +294,22 @@
> > >  	status = "okay";
> > >  };
> > >
> > > +&pcie0 {
> > > +	perst-gpios = <&sysgpio 26 GPIO_ACTIVE_LOW>;
> > > +	phys = <&pciephy0>;
> > > +	pinctrl-names = "default";
> > > +	pinctrl-0 = <&pcie0_pins>;
> > > +	status = "okay";
> > > +};
> > > +
> > > +&pcie1 {
> > > +	perst-gpios = <&sysgpio 28 GPIO_ACTIVE_LOW>;
> > > +	phys = <&pciephy1>;
> > > +	pinctrl-names = "default";
> > > +	pinctrl-0 = <&pcie1_pins>;
> > > +	status = "okay";
> > > +};
> > 
> > Do all 3 of the mars, star64 and visionfive 2 have both PCIe ports exposed? I
> > assume if one does, all does, since they're basically identical?
> 
> Visionfive 2 and milkv mars are all the same. Star64 do NOT enable PCIe0, PCIe1 pins are the same.

This patch adds both PCIe instances for the Star64 though, since that
also includes jh7110-common.dtsi. I think you need to enable these in
the board dts files instead?

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