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Message-Id: <20240612-6-10-rocket-v1-3-060e48eea250@tomeuvizoso.net>
Date: Wed, 12 Jun 2024 15:52:56 +0200
From: Tomeu Vizoso <tomeu@...euvizoso.net>
To: Joerg Roedel <joro@...tes.org>, Will Deacon <will@...nel.org>,
Robin Murphy <robin.murphy@....com>, Heiko Stuebner <heiko@...ech.de>,
Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, Oded Gabbay <ogabbay@...nel.org>,
Tomeu Vizoso <tomeu.vizoso@...euvizoso.net>,
David Airlie <airlied@...il.com>, Daniel Vetter <daniel@...ll.ch>,
Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>,
Maxime Ripard <mripard@...nel.org>, Thomas Zimmermann <tzimmermann@...e.de>,
Philipp Zabel <p.zabel@...gutronix.de>,
Sumit Semwal <sumit.semwal@...aro.org>,
Christian König <christian.koenig@....com>
Cc: iommu@...ts.linux.dev, linux-arm-kernel@...ts.infradead.org,
linux-rockchip@...ts.infradead.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org, dri-devel@...ts.freedesktop.org,
linux-media@...r.kernel.org, linaro-mm-sig@...ts.linaro.org,
Tomeu Vizoso <tomeu@...euvizoso.net>
Subject: [PATCH 3/9] dt-bindings: mailbox: rockchip,rknn: Add bindings
Add the bindings for the Neural Processing Unit IP from Rockchip.
Signed-off-by: Tomeu Vizoso <tomeu@...euvizoso.net>
---
.../devicetree/bindings/npu/rockchip,rknn.yaml | 123 +++++++++++++++++++++
1 file changed, 123 insertions(+)
diff --git a/Documentation/devicetree/bindings/npu/rockchip,rknn.yaml b/Documentation/devicetree/bindings/npu/rockchip,rknn.yaml
new file mode 100644
index 000000000000..570a4889c11c
--- /dev/null
+++ b/Documentation/devicetree/bindings/npu/rockchip,rknn.yaml
@@ -0,0 +1,123 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/npu/rockchip,rknn.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Neural Processing Unit IP from Rockchip, based on NVIDIA's NVDLA
+
+maintainers:
+ - Tomeu Vizoso <tomeu@...euvizoso.net>
+
+description: |+
+ Rockchip IP for accelerating inference of neural networks, based on NVIDIA's open source NVDLA IP.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - rockchip,rk3588-rknn
+ - const: rockchip,rknn
+
+ reg:
+ description: Base registers for NPU cores
+ minItems: 1
+ maxItems: 20
+
+ interrupts:
+ minItems: 1
+ maxItems: 20
+
+ interrupt-names:
+ minItems: 1
+ maxItems: 20
+
+ clocks:
+ minItems: 1
+ maxItems: 20
+
+ clock-names:
+ minItems: 1
+ maxItems: 20
+
+ assigned-clocks:
+ maxItems: 1
+
+ assigned-clock-rates:
+ maxItems: 1
+
+ resets:
+ minItems: 1
+ maxItems: 20
+
+ reset-names:
+ minItems: 1
+ maxItems: 20
+
+ power-domains:
+ minItems: 1
+ maxItems: 20
+
+ power-domain-names:
+ minItems: 1
+ maxItems: 20
+
+ iommus:
+ items:
+ - description: IOMMU for all cores
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-names
+ - clocks
+ - clock-names
+ - assigned-clocks
+ - assigned-clock-rates
+ - resets
+ - reset-names
+ - power-domains
+ - power-domain-names
+ - iommus
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ bus {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ rknn: npu@...b0000 {
+ compatible = "rockchip,rk3588-rknn", "rockchip,rknn";
+ reg = <0x0 0xfdab0000 0x0 0x9000>,
+ <0x0 0xfdac0000 0x0 0x9000>,
+ <0x0 0xfdad0000 0x0 0x9000>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "npu0_irq", "npu1_irq", "npu2_irq";
+ clocks = <&scmi_clk 0>, <&cru 1>,
+ <&cru 2>, <&cru 3>,
+ <&cru 4>, <&cru 5>,
+ <&cru 6>, <&cru 7>;
+ clock-names = "clk_npu",
+ "aclk0", "aclk1", "aclk2",
+ "hclk0", "hclk1", "hclk2",
+ "pclk";
+ assigned-clocks = <&scmi_clk 0>;
+ assigned-clock-rates = <200000000>;
+ resets = <&cru 0>, <&cru 1>, <&cru 2>,
+ <&cru 3>, <&cru 4>, <&cru 5>;
+ reset-names = "srst_a0", "srst_a1", "srst_a2",
+ "srst_h0", "srst_h1", "srst_h2";
+ power-domains = <&power 0>, <&power 1>, <&power 2>;
+ power-domain-names = "npu0", "npu1", "npu2";
+ iommus = <&rknpu_mmu>;
+ status = "disabled";
+ };
+ };
+...
--
2.45.2
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