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Message-ID:
 <IA1PR20MB4953B4A44227ED6431888709BBCD2@IA1PR20MB4953.namprd20.prod.outlook.com>
Date: Mon, 17 Jun 2024 11:36:32 +0800
From: Inochi Amaoto <inochiama@...look.com>
To: Yixun Lan <dlan@...too.org>, 
	Thomas Bonnefille <thomas.bonnefille@...tlin.com>
Cc: Inochi Amaoto <inochiama@...look.com>, 
	Jisheng Zhang <jszhang@...nel.org>, Rob Herring <robh@...nel.org>, 
	Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, 
	Paul Walmsley <paul.walmsley@...ive.com>, Chen Wang <unicorn_wang@...look.com>, 
	Chao Wei <chao.wei@...hgo.com>, Albert Ou <aou@...s.berkeley.edu>, 
	Palmer Dabbelt <palmer@...belt.com>, Samuel Holland <samuel.holland@...ive.com>, 
	Thomas Gleixner <tglx@...utronix.de>, Daniel Lezcano <daniel.lezcano@...aro.org>, 
	Thomas Petazzoni <thomas.petazzoni@...tlin.com>, Miquèl Raynal <miquel.raynal@...tlin.com>, 
	linux-kernel@...r.kernel.org, devicetree@...r.kernel.org, linux-riscv@...ts.infradead.org
Subject: Re: [PATCH v2 1/6] riscv: dts: sophgo: Put sdhci compatible in dt of
 specific SoC

On Sun, Jun 16, 2024 at 11:58:29PM GMT, Yixun Lan wrote:
> Hi
> 
> On 18:47 Wed 12 Jun     , Inochi Amaoto wrote:
> > On Wed, Jun 12, 2024 at 10:02:31AM GMT, Thomas Bonnefille wrote:
> > > Remove SDHCI compatible for CV1800b from common dtsi file to put it in
> > > the specific dtsi file of the CV1800b.
> > > This commits aims at following the same guidelines as in the other nodes
> > > of the CV18XX family.
> is there any URL of guideline? or did I miss anything
> couldn't find any discussion about this in v1
> 

No, it seems like that this is a new change from Thomas.

> > > 
> > > Signed-off-by: Thomas Bonnefille <thomas.bonnefille@...tlin.com>
> > > ---
> > >  arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 4 ++++
> > >  arch/riscv/boot/dts/sophgo/cv18xx.dtsi  | 1 -
> > >  2 files changed, 4 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> > > index ec9530972ae2..b9cd51457b4c 100644
> > > --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> > > +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> > > @@ -25,3 +25,7 @@ &clint {
> > >  &clk {
> > >  	compatible = "sophgo,cv1800-clk";
> > >  };
> > > +
> > > +&sdhci0 {
> > > +	compatible = "sophgo,cv1800b-dwcmshc";
> > > +};
> > > diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
> > > index 891932ae470f..7247c7c3013c 100644
> > > --- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
> > > +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
> > > @@ -288,7 +288,6 @@ uart4: serial@...0000 {
> > >  		};
> > >  
> > >  		sdhci0: mmc@...0000 {
> > > -			compatible = "sophgo,cv1800b-dwcmshc";
> > >  			reg = <0x4310000 0x1000>;
> > >  			interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
> > >  			clocks = <&clk CLK_AXI4_SD0>,
> > > 
> > > -- 
> > > 2.45.2
> > > 
> > 
> > Hi, Jisheng,
> > 
> > Is this change necessary? IIRC, the sdhci is the same across 
> > the whole series.
> I tend to agree with Inochi here, if it's same across all SoC, then no bother to
> split, it will cause more trouble to maintain..
> 
> > 
> > Regards,
> > Inochi
> 
> -- 
> Yixun Lan (dlan)
> Gentoo Linux Developer
> GPG Key ID AABEFD55

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