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Message-ID: <b5c1536b-1d8e-4d57-aeda-c5d06a2793bd@infradead.org>
Date: Tue, 18 Jun 2024 16:06:57 -0700
From: Randy Dunlap <rdunlap@...radead.org>
To: Maxwell Bland <mbland@...orola.com>, linux-mm@...ck.org
Cc: Catalin Marinas <catalin.marinas@....com>, Will Deacon <will@...nel.org>,
Jonathan Corbet <corbet@....net>, Andrew Morton <akpm@...ux-foundation.org>,
Ard Biesheuvel <ardb@...nel.org>, Mark Rutland <mark.rutland@....com>,
Christophe Leroy <christophe.leroy@...roup.eu>,
Alexandre Ghiti <alexghiti@...osinc.com>,
linux-arm-kernel@...ts.infradead.org, linux-doc@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH v4 5/5] arm64: add attrs and format to ptdump document
Hi,-
On 6/18/24 7:43 AM, Maxwell Bland wrote:
> Update the ptdump content with a precise explanation of the attribute
> symbols and the identical-entry coalescing implicit in the code.
>
> Remove unnecessary layout example given the existing cat example,
> and opt instead for a precise, clear explantination of address markers,
explanation
> format, attributes.
>
> Update example to match the new cosmetic and intermediate-directory
> printing changes.
>
> Signed-off-by: Maxwell Bland <mbland@...orola.com>
> ---
> Documentation/arch/arm64/ptdump.rst | 126 ++++++++++++++--------------
> 1 file changed, 61 insertions(+), 65 deletions(-)
>
> diff --git a/Documentation/arch/arm64/ptdump.rst b/Documentation/arch/arm64/ptdump.rst
> index 5dcfc5d7cddf..fee7600dd4d1 100644
> --- a/Documentation/arch/arm64/ptdump.rst
> +++ b/Documentation/arch/arm64/ptdump.rst
> @@ -29,68 +29,64 @@ configurations and mount debugfs::
> mount -t debugfs nodev /sys/kernel/debug
> cat /sys/kernel/debug/kernel_page_tables
>
> -On analysing the output of ``cat /sys/kernel/debug/kernel_page_tables``
> -one can derive information about the virtual address range of the entry,
> -followed by size of the memory region covered by this entry, the
> -hierarchical structure of the page tables and finally the attributes
> -associated with each page. The page attributes provide information about
> -access permissions, execution capability, type of mapping such as leaf
> -level PTE or block level PGD, PMD and PUD, and access status of a page
> -within the kernel memory. Assessing these attributes can assist in
> -understanding the memory layout, access patterns and security
> -characteristics of the kernel pages.
> -
> -Kernel virtual memory layout example::
> -
> - start address end address size attributes
> - +---------------------------------------------------------------------------------------+
> - | ---[ Linear Mapping start ]---------------------------------------------------------- |
> - | .................. |
> - | 0xfff0000000000000-0xfff0000000210000 2112K PTE RW NX SHD AF UXN MEM/NORMAL-TAGGED |
> - | 0xfff0000000210000-0xfff0000001c00000 26560K PTE ro NX SHD AF UXN MEM/NORMAL |
> - | .................. |
> - | ---[ Linear Mapping end ]------------------------------------------------------------ |
> - +---------------------------------------------------------------------------------------+
> - | ---[ Modules start ]----------------------------------------------------------------- |
> - | .................. |
> - | 0xffff800000000000-0xffff800008000000 128M PTE |
> - | .................. |
> - | ---[ Modules end ]------------------------------------------------------------------- |
> - +---------------------------------------------------------------------------------------+
> - | ---[ vmalloc() area ]---------------------------------------------------------------- |
> - | .................. |
> - | 0xffff800008010000-0xffff800008200000 1984K PTE ro x SHD AF UXN MEM/NORMAL |
> - | 0xffff800008200000-0xffff800008e00000 12M PTE ro x SHD AF CON UXN MEM/NORMAL |
> - | .................. |
> - | ---[ vmalloc() end ]----------------------------------------------------------------- |
> - +---------------------------------------------------------------------------------------+
> - | ---[ Fixmap start ]------------------------------------------------------------------ |
> - | .................. |
> - | 0xfffffbfffdb80000-0xfffffbfffdb90000 64K PTE ro x SHD AF UXN MEM/NORMAL |
> - | 0xfffffbfffdb90000-0xfffffbfffdba0000 64K PTE ro NX SHD AF UXN MEM/NORMAL |
> - | .................. |
> - | ---[ Fixmap end ]-------------------------------------------------------------------- |
> - +---------------------------------------------------------------------------------------+
> - | ---[ PCI I/O start ]----------------------------------------------------------------- |
> - | .................. |
> - | 0xfffffbfffe800000-0xfffffbffff800000 16M PTE |
> - | .................. |
> - | ---[ PCI I/O end ]------------------------------------------------------------------- |
> - +---------------------------------------------------------------------------------------+
> - | ---[ vmemmap start ]----------------------------------------------------------------- |
> - | .................. |
> - | 0xfffffc0002000000-0xfffffc0002200000 2M PTE RW NX SHD AF UXN MEM/NORMAL |
> - | 0xfffffc0002200000-0xfffffc0020000000 478M PTE |
> - | .................. |
> - | ---[ vmemmap end ]------------------------------------------------------------------- |
> - +---------------------------------------------------------------------------------------+
> -
> -``cat /sys/kernel/debug/kernel_page_tables`` output::
> -
> - 0xfff0000001c00000-0xfff0000080000000 2020M PTE RW NX SHD AF UXN MEM/NORMAL-TAGGED
> - 0xfff0000080000000-0xfff0000800000000 30G PMD
> - 0xfff0000800000000-0xfff0000800700000 7M PTE RW NX SHD AF UXN MEM/NORMAL-TAGGED
> - 0xfff0000800700000-0xfff0000800710000 64K PTE ro NX SHD AF UXN MEM/NORMAL-TAGGED
> - 0xfff0000800710000-0xfff0000880000000 2089920K PTE RW NX SHD AF UXN MEM/NORMAL-TAGGED
> - 0xfff0000880000000-0xfff0040000000000 4062G PMD
> - 0xfff0040000000000-0xffff800000000000 3964T PGD
> +``/sys/kernel/debug/kernel_page_tables`` provides a line of information
> +for each group of page table entries sharing the same attributes and
> +type of mapping, i.e. leaf level PTE or block level PGD, PMD, and PUD.
> +Assessing these attributes can assist in determining memory layout,
> +access patterns and security characteristics of the kernel pages.
> +
> +Lines are formatted as follows::
> +
> + <start_vaddr>-<end_vaddr> <size> <type> <attributes>
> +
> +Note that the set of attributes, and therefore formatting, is not
> +equivalent between leaf and non-leaf entries. For example, PMD entries
> +can support the PXNTable permission bit and do not share that same set
> +of attributes as leaf level PTE entries.
> +
> +The following attributes are presently supported::
> +
> +F Entry is invalid
> +USER Memory is user mapped
> +ro Memory is read-only
> +RW Memory is read-write
> +NX Memory is privileged execute never
> +x Memory is privileged executable
Please use tabs above for indentation, like the other lines.
Why lower case x and ro but upper case for the others?
> +SHD Memory is shared
> +AF Entry accessed flag is set
> +NG Entry Not-Global flag is set
> +CON Entry contiguous bit is set
> +UXN Memory is unprivileged execute never
> +GP Memory supports BTI
Most of the abbreviations make some sense, but not that one (IMHO). ;)
> +TBL Entry is a table descriptor
> +BLK Entry is a block descriptor
> +NXTbl Entry's referenced table is PXN
> +UXNTbl Entry's referenced table is unprivileged execute never
> +DEVICE/* Entry is device memory, see ARM reference for types
> +MEM/* Entry is non-device memory, see ARM reference for types
> +
> +The beginning and end of each region is also delineated by a single line
> +tag in the following format::
> +
> + ---[ <marker_name> ]---
> +
> +With supported address markers including the kernel's linear mapping,
> +kasan shadow memory, kernel modules memory, vmalloc memory, PCI I/O
> +memory, and the kernel's fixmap region.
> +
> +Example ``cat /sys/kernel/debug/kernel_page_tables`` output::
> +
> +---[ Linear Mapping start ]---
> +0xffff000000000000-0xffff31ffffffffff 50T PGD
> +0xffff320000000000-0xffffffffffffffff 206T PGD TBL RW x NXTbl UXNTbl MEM/NORMAL
> + 0xffff320000000000-0xffff3251ffffffff 328G PUD
> + 0xffff325200000000-0xffff32523fffffff 1G PUD TBL RW x NXTbl UXNTbl MEM/NORMAL
> + 0xffff325200000000-0xffff3252001fffff 2M PMD TBL RW x NXTbl UXNTbl MEM/NORMAL
> + 0xffff325200000000-0xffff3252001fffff 2M PTE RW NX SHD AF NG UXN MEM/NORMAL-TAGGED
> + 0xffff325200200000-0xffff3252003fffff 2M PMD TBL RW x NXTbl UXNTbl MEM/NORMAL
> + 0xffff325200200000-0xffff32520020ffff 64K PTE RW NX SHD AF NG UXN MEM/NORMAL-TAGGED
> + 0xffff325200210000-0xffff3252003fffff 1984K PTE ro NX SHD AF NG UXN MEM/NORMAL
> + 0xffff325200400000-0xffff325201dfffff 26M PMD BLK ro SHD AF NG NX UXN MEM/NORMAL
> + 0xffff325201e00000-0xffff325201ffffff 2M PMD TBL RW x NXTbl UXNTbl MEM/NORMAL
> + 0xffff325201e00000-0xffff325201e0ffff 64K PTE ro NX SHD AF NG UXN MEM/NORMAL
> + 0xffff325201e10000-0xffff325201ffffff 1984K PTE RW NX SHD AF NG UXN MEM/NORMAL-TAGGED
--
thanks.
~Randy
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