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Message-ID: <0b53607e-03f4-4f3e-9332-c9f4c43ac88b@amd.com>
Date: Wed, 19 Jun 2024 21:26:34 +0530
From: Ravi Bangoria <ravi.bangoria@....com>
To: Namhyung Kim <namhyung@...nel.org>
Cc: acme@...nel.org, irogers@...gle.com, peterz@...radead.org,
 mingo@...hat.com, mark.rutland@....com, alexander.shishkin@...ux.intel.com,
 jolsa@...nel.org, adrian.hunter@...el.com, kan.liang@...ux.intel.com,
 yangjihong1@...wei.com, linux-kernel@...r.kernel.org,
 linux-perf-users@...r.kernel.org, sandipan.das@....com,
 ananth.narayan@....com, santosh.shukla@....com,
 Stephane Eranian <eranian@...gle.com>, Ravi Bangoria <ravi.bangoria@....com>
Subject: Re: [PATCH] perf doc: Add AMD IBS usage document

>> +IBS Fetch PMU
>> +~~~~~~~~~~~~~
>> +
>> +Similar commands can be used with Fetch PMU as well.
>> +
>> +System-wide profile, fetch ops event, sampling period: 100000
>> +
>> +       $ sudo perf record -e ibs_fetch// -c 100000 -a
>> +
>> +System-wide profile, fetch ops event, sampling period: 100000, Random enable
> 
> Can you please add a brief description of what 'random enable' means?

Sure, here is the detail about RandEn bit:

Sample period value in IBS Fetch PMU must be multiple of 16. IBS hardware
internally sets pseudo-random value in [3:0] bits when RandEn bit is set.
This variability will help in cases like long running loops where IBS
Fetch PMU is tagging the same instruction over and over because of the
fixed sample period.

Thanks for the review,
Ravi

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