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Date: Fri, 21 Jun 2024 12:29:15 +0100
From: <daire.mcnamara@...rochip.com>
To: <linux-pci@...r.kernel.org>, <devicetree@...r.kernel.org>
CC: <conor.dooley@...rochip.com>, <lpieralisi@...nel.org>, <kw@...ux.com>,
<robh@...nel.org>, <bhelgaas@...gle.com>, <linux-kernel@...r.kernel.org>,
<linux-riscv@...ts.infradead.org>, <krzk+dt@...nel.org>,
<conor+dt@...nel.org>, <daire.mcnamara@...rochip.com>,
<ilpo.jarvinen@...ux.intel.com>
Subject: [PATCH v4 3/3] dt-bindings: PCI: microchip,pcie-host: allow dma-noncoherent
From: Conor Dooley <conor.dooley@...rochip.com>
PolarFire SoC may be configured in a way that requires non-coherent DMA
handling. On RISC-V, buses are coherent by default & the dma-noncoherent
property is required to denote buses or devices that are non-coherent.
Signed-off-by: Conor Dooley <conor.dooley@...rochip.com>
Signed-off-by: Daire McNamara <daire.mcnamara@...rochip.com>
---
Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml
index f7a3c2636355..c84e1ae20532 100644
--- a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml
+++ b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml
@@ -52,6 +52,8 @@ properties:
items:
pattern: '^fic[0-3]$'
+ dma-noncoherent: true
+
interrupts:
minItems: 1
items:
--
2.34.1
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