linux-kernel - Re: [PATCH v4 1/3] PCI: microchip: Fix outbound address translation tables

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Message-ID: <395f27f6-d263-71d3-acbd-b1872bc48fa3@linux.intel.com>
Date: Sun, 23 Jun 2024 20:02:35 +0300 (EEST)
From: Ilpo Järvinen <ilpo.jarvinen@...ux.intel.com>
To: daire.mcnamara@...rochip.com
cc: linux-pci@...r.kernel.org, devicetree@...r.kernel.org, 
    conor.dooley@...rochip.com, lpieralisi@...nel.org, kw@...ux.com, 
    robh@...nel.org, bhelgaas@...gle.com, LKML <linux-kernel@...r.kernel.org>, 
    linux-riscv@...ts.infradead.org, krzk+dt@...nel.org, conor+dt@...nel.org
Subject: Re: [PATCH v4 1/3] PCI: microchip: Fix outbound address translation
 tables

On Fri, 21 Jun 2024, daire.mcnamara@...rochip.com wrote:

> From: Daire McNamara <daire.mcnamara@...rochip.com>
> 
> On Microchip PolarFire SoC (MPFS) the PCIe Root Port can be behind one of
> three general-purpose Fabric Interface Controller (FIC) buses that
> encapsulate an AXI-M interface. That FIC is responsible for managing
> the translations of the upper 32-bits of the AXI-M address. On MPFS,
> the Root Port driver needs to take account of that outbound address
> translation done by the parent FIC bus before setting up its own
> outbound address translation tables.  In all cases on MPFS,
> the remaining outbound address translation tables are 32-bit only.
> 
> Limit the outbound address translation tables to 32-bit only.
> 
> Fixes: 6f15a9c9f941 ("PCI: microchip: Add Microchip Polarfire PCIe controller driver")
> 
> Signed-off-by: Daire McNamara <daire.mcnamara@...rochip.com>
> ---
>  drivers/pci/controller/pcie-microchip-host.c | 10 +++++-----
>  1 file changed, 5 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/pci/controller/pcie-microchip-host.c b/drivers/pci/controller/pcie-microchip-host.c
> index 137fb8570ba2..853adce24492 100644
> --- a/drivers/pci/controller/pcie-microchip-host.c
> +++ b/drivers/pci/controller/pcie-microchip-host.c
> @@ -933,7 +933,7 @@ static int mc_pcie_init_irq_domains(struct mc_pcie *port)
>  
>  static void mc_pcie_setup_window(void __iomem *bridge_base_addr, u32 index,
>  				 phys_addr_t axi_addr, phys_addr_t pci_addr,
> -				 size_t size)
> +				 u64 size)
>  {
>  	u32 atr_sz = ilog2(size) - 1;
>  	u32 val;
> @@ -983,7 +983,8 @@ static int mc_pcie_setup_windows(struct platform_device *pdev,
>  		if (resource_type(entry->res) == IORESOURCE_MEM) {
>  			pci_addr = entry->res->start - entry->offset;
>  			mc_pcie_setup_window(bridge_base_addr, index,
> -					     entry->res->start, pci_addr,
> +					     entry->res->start & 0xffffffff,
> +					     pci_addr,
>  					     resource_size(entry->res));
>  			index++;
>  		}
> @@ -1117,9 +1118,8 @@ static int mc_platform_init(struct pci_config_window *cfg)
>  	int ret;
>  
>  	/* Configure address translation table 0 for PCIe config space */
> -	mc_pcie_setup_window(bridge_base_addr, 0, cfg->res.start,
> -			     cfg->res.start,
> -			     resource_size(&cfg->res));
> +	mc_pcie_setup_window(bridge_base_addr, 0, cfg->res.start & 0xffffffff,
> +			     0, resource_size(&cfg->res));
>  
>  	/* Need some fixups in config space */
>  	mc_pcie_enable_msi(port, cfg->win);

I had some comments for this patch too none of which are addressed by the 
the v4?

-- 
 i.