linux-kernel - Re: [PATCH v3 2/6] phy: exynos5-usbdrd: support isolating HS and SS ports independently

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Date: Fri, 21 Jun 2024 17:02:50 -0700
From: William McVicker <willmcvicker@...gle.com>
To: André Draszik <andre.draszik@...aro.org>
Cc: Vinod Koul <vkoul@...nel.org>,
	Kishon Vijay Abraham I <kishon@...nel.org>,
	Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>,
	Peter Griffin <peter.griffin@...aro.org>,
	Marek Szyprowski <m.szyprowski@...sung.com>,
	Sylwester Nawrocki <s.nawrocki@...sung.com>,
	Alim Akhtar <alim.akhtar@...sung.com>,
	Sam Protsenko <semen.protsenko@...aro.org>,
	Krzysztof Kozlowski <krzk@...nel.org>,
	Tudor Ambarus <tudor.ambarus@...aro.org>,
	Roy Luo <royluo@...gle.com>, kernel-team@...roid.com,
	linux-phy@...ts.infradead.org, devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
	linux-samsung-soc@...r.kernel.org
Subject: Re: [PATCH v3 2/6] phy: exynos5-usbdrd: support isolating HS and SS
 ports independently

On 06/17/2024, André Draszik wrote:
> Some versions of this IP have been integrated using separate PMU power
> control registers for the HS and SS parts. One example is the Google
> Tensor gs101 SoC.
> 
> Such SoCs can now set pmu_offset_usbdrd0_phy_ss in their
> exynos5_usbdrd_phy_drvdata for the SS phy to the appropriate value.
> 
> The existing 'usbdrdphy' alias can not be used in this case because
> that is meant for determining the correct PMU offset if multiple
> distinct PHYs exist in the system (as opposed to one PHY with multiple
> isolators).
> 
> Signed-off-by: André Draszik <andre.draszik@...aro.org>

Tested-by: Will McVicker <willmcvicker@...gle.com>

[...]

Thanks,
Will