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Message-ID: <ZnYU4TRR3gUbadWR@google.com>
Date: Fri, 21 Jun 2024 17:03:45 -0700
From: William McVicker <willmcvicker@...gle.com>
To: André Draszik <andre.draszik@...aro.org>
Cc: Vinod Koul <vkoul@...nel.org>,
	Kishon Vijay Abraham I <kishon@...nel.org>,
	Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>,
	Peter Griffin <peter.griffin@...aro.org>,
	Marek Szyprowski <m.szyprowski@...sung.com>,
	Sylwester Nawrocki <s.nawrocki@...sung.com>,
	Alim Akhtar <alim.akhtar@...sung.com>,
	Sam Protsenko <semen.protsenko@...aro.org>,
	Krzysztof Kozlowski <krzk@...nel.org>,
	Tudor Ambarus <tudor.ambarus@...aro.org>,
	Roy Luo <royluo@...gle.com>, kernel-team@...roid.com,
	linux-phy@...ts.infradead.org, devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
	linux-samsung-soc@...r.kernel.org
Subject: Re: [PATCH v3 4/6] phy: exynos5-usbdrd: convert (phy) register
 access clock to clk_bulk

On 06/17/2024, André Draszik wrote:
> In preparation for support for additional platforms, convert the phy
> register access clock to using the clk_bulk interfaces.
> 
> Newer SoCs like Google Tensor gs101 require additional clocks for
> access to additional (different) register areas (PHY, PMA, PCS), and
> converting to clk_bulk simplifies addition of those extra clocks.
> 
> Signed-off-by: André Draszik <andre.draszik@...aro.org>

Tested-by: Will McVicker <willmcvicker@...gle.com>

[...]

Thanks,
Will

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