[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-ID: <ZnblsA42uTfU8Yx5@yilunxu-OptiPlex-7050>
Date: Sat, 22 Jun 2024 22:54:40 +0800
From: Xu Yilun <yilun.xu@...ux.intel.com>
To: Wolfram Sang <wsa+renesas@...g-engineering.com>
Cc: linux-kernel@...r.kernel.org, Michal Simek <michal.simek@....com>,
Moritz Fischer <mdf@...nel.org>, Wu Hao <hao.wu@...el.com>,
Xu Yilun <yilun.xu@...el.com>, Tom Rix <trix@...hat.com>,
linux-fpga@...r.kernel.org, linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH v2 2/2] fpga: zynq-fpga: use 'time_left' variable with
wait_for_completion_timeout()
On Thu, Jun 20, 2024 at 01:50:22PM +0200, Wolfram Sang wrote:
Please check the same shortlog problem for all your patches
Thanks,
Yilun
> There is a confusing pattern in the kernel to use a variable named
> 'timeout' to store the result of wait_for_completion_timeout() causing
> patterns like:
>
> timeout = wait_for_completion_timeout(...)
> if (!timeout) return -ETIMEDOUT;
>
> with all kinds of permutations. Use 'time_left' as a variable to make
> the code self explaining.
>
> Signed-off-by: Wolfram Sang <wsa+renesas@...g-engineering.com>
> Acked-by: Michal Simek <michal.simek@....com>
> ---
>
> Change since v1: added ack (Thanks Michal)
>
> drivers/fpga/zynq-fpga.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/fpga/zynq-fpga.c b/drivers/fpga/zynq-fpga.c
> index 0ac93183d201..4db3d80e10b0 100644
> --- a/drivers/fpga/zynq-fpga.c
> +++ b/drivers/fpga/zynq-fpga.c
> @@ -387,7 +387,7 @@ static int zynq_fpga_ops_write(struct fpga_manager *mgr, struct sg_table *sgt)
> const char *why;
> int err;
> u32 intr_status;
> - unsigned long timeout;
> + unsigned long time_left;
> unsigned long flags;
> struct scatterlist *sg;
> int i;
> @@ -427,8 +427,8 @@ static int zynq_fpga_ops_write(struct fpga_manager *mgr, struct sg_table *sgt)
> zynq_step_dma(priv);
> spin_unlock_irqrestore(&priv->dma_lock, flags);
>
> - timeout = wait_for_completion_timeout(&priv->dma_done,
> - msecs_to_jiffies(DMA_TIMEOUT_MS));
> + time_left = wait_for_completion_timeout(&priv->dma_done,
> + msecs_to_jiffies(DMA_TIMEOUT_MS));
>
> spin_lock_irqsave(&priv->dma_lock, flags);
> zynq_fpga_set_irq(priv, 0);
> @@ -452,7 +452,7 @@ static int zynq_fpga_ops_write(struct fpga_manager *mgr, struct sg_table *sgt)
>
> if (priv->cur_sg ||
> !((intr_status & IXR_D_P_DONE_MASK) == IXR_D_P_DONE_MASK)) {
> - if (timeout == 0)
> + if (time_left == 0)
> why = "DMA timed out";
> else
> why = "DMA did not complete";
> --
> 2.43.0
>
>
Powered by blists - more mailing lists