linux-kernel - Re: [PATCH 5/5] clk: qcom: dispcc-sm8650: Update the GDSC wait

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Message-ID: <c2c14080-25bd-4732-bf9c-0a9d385866f4@linaro.org>
Date: Mon, 24 Jun 2024 09:57:27 +0200
From: Neil Armstrong <neil.armstrong@...aro.org>
To: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
Cc: Bjorn Andersson <andersson@...nel.org>,
 Michael Turquette <mturquette@...libre.com>, Stephen Boyd
 <sboyd@...nel.org>, Konrad Dybcio <konrad.dybcio@...aro.org>,
 Taniya Das <quic_tdas@...cinc.com>, linux-arm-msm@...r.kernel.org,
 linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 5/5] clk: qcom: dispcc-sm8650: Update the GDSC wait_val
 fields and flags

On 21/06/2024 23:39, Dmitry Baryshkov wrote:
> On Fri, Jun 21, 2024 at 04:01:18PM GMT, Neil Armstrong wrote:
>> Update the GDSC wait_val fields and flags as per the default hardware values.
> 
> If they are default, do we need to program them?
> 
>> Add the missing POLL_CFG_GDSCR flag.
> 
> I'd say, two distinct fixes.

I'll drop the wait_val fields changes and only add the missing flags.

Neil

> 
>>
>> Fixes: 9e939f008338 ("clk: qcom: add the SM8650 Display Clock Controller driver")
>> Signed-off-by: Neil Armstrong <neil.armstrong@...aro.org>
>> ---
>>   drivers/clk/qcom/dispcc-sm8650.c | 10 ++++++++--
>>   1 file changed, 8 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/clk/qcom/dispcc-sm8650.c b/drivers/clk/qcom/dispcc-sm8650.c
>> index d88eebb32575..2da3c11b0c3d 100644
>> --- a/drivers/clk/qcom/dispcc-sm8650.c
>> +++ b/drivers/clk/qcom/dispcc-sm8650.c
>> @@ -1604,20 +1604,26 @@ static struct clk_branch disp_cc_sleep_clk = {
>>   
>>   static struct gdsc mdss_gdsc = {
>>   	.gdscr = 0x9000,
>> +	.en_rest_wait_val = 0x2,
>> +	.en_few_wait_val = 0x2,
>> +	.clk_dis_wait_val = 0xf,
>>   	.pd = {
>>   		.name = "mdss_gdsc",
>>   	},
>>   	.pwrsts = PWRSTS_OFF_ON,
>> -	.flags = HW_CTRL | RETAIN_FF_ENABLE,
>> +	.flags = POLL_CFG_GDSCR | HW_CTRL | RETAIN_FF_ENABLE,
>>   };
>>   
>>   static struct gdsc mdss_int2_gdsc = {
>>   	.gdscr = 0xb000,
>> +	.en_rest_wait_val = 0x2,
>> +	.en_few_wait_val = 0x2,
>> +	.clk_dis_wait_val = 0xf,
>>   	.pd = {
>>   		.name = "mdss_int2_gdsc",
>>   	},
>>   	.pwrsts = PWRSTS_OFF_ON,
>> -	.flags = HW_CTRL | RETAIN_FF_ENABLE,
>> +	.flags = POLL_CFG_GDSCR | HW_CTRL | RETAIN_FF_ENABLE,
>>   };
>>   
>>   static struct clk_regmap *disp_cc_sm8650_clocks[] = {
>>
>> -- 
>> 2.34.1
>>
>