linux-kernel - Re: [PATCH v5 1/3] PCI: microchip: Fix outbound address translation tables

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Date: Tue, 25 Jun 2024 17:26:12 +0100
From: Conor Dooley <conor@...nel.org>
To: daire.mcnamara@...rochip.com
Cc: linux-pci@...r.kernel.org, devicetree@...r.kernel.org,
	conor.dooley@...rochip.com, lpieralisi@...nel.org, kw@...ux.com,
	robh@...nel.org, bhelgaas@...gle.com, linux-kernel@...r.kernel.org,
	linux-riscv@...ts.infradead.org, krzk+dt@...nel.org,
	conor+dt@...nel.org, ilpo.jarvinen@...ux.intel.com
Subject: Re: [PATCH v5 1/3] PCI: microchip: Fix outbound address translation
 tables

On Tue, Jun 25, 2024 at 01:38:43PM +0100, daire.mcnamara@...rochip.com wrote:
> From: Daire McNamara <daire.mcnamara@...rochip.com>
> 
> On Microchip PolarFire SoC (MPFS) the PCIe Root Port can be behind one of
> three general-purpose Fabric Interface Controller (FIC) buses that
> encapsulate an AXI-M interface. That FIC is responsible for managing
> the translations of the upper 32-bits of the AXI-M address. On MPFS,
> the Root Port driver needs to take account of that outbound address
> translation done by the parent FIC bus before setting up its own
> outbound address translation tables.  In all cases on MPFS,
> the remaining outbound address translation tables are 32-bit only.
> 
> Limit the outbound address translation tables to 32-bit only.
> 
> This necessitates changing a size_t in mc_pcie_setup_window
> to a resource_size_t to avoid a compile error on 32-bit platforms.
> 
> Fixes: 6f15a9c9f941 ("PCI: microchip: Add Microchip Polarfire PCIe controller driver")
> Signed-off-by: Daire McNamara <daire.mcnamara@...rochip.com>

Acked-by: Conor Dooley <conor.dooley@...rochip.com>

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