linux-kernel - Re: [PATCH v5 2/3] PCI: microchip: Fix inbound address translation tables

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Date: Tue, 25 Jun 2024 17:26:36 +0100
From: Conor Dooley <conor@...nel.org>
To: daire.mcnamara@...rochip.com
Cc: linux-pci@...r.kernel.org, devicetree@...r.kernel.org,
	conor.dooley@...rochip.com, lpieralisi@...nel.org, kw@...ux.com,
	robh@...nel.org, bhelgaas@...gle.com, linux-kernel@...r.kernel.org,
	linux-riscv@...ts.infradead.org, krzk+dt@...nel.org,
	conor+dt@...nel.org, ilpo.jarvinen@...ux.intel.com
Subject: Re: [PATCH v5 2/3] PCI: microchip: Fix inbound address translation
 tables

On Tue, Jun 25, 2024 at 01:38:44PM +0100, daire.mcnamara@...rochip.com wrote:
> From: Daire McNamara <daire.mcnamara@...rochip.com>
> 
> On Microchip PolarFire SoC the PCIe Root Port can be behind one of three
> general purpose Fabric Interface Controller (FIC) buses that encapsulates
> an AXI-S bus. Depending on which FIC(s) the Root Port is connected
> through to CPU space, and what address translation is done by that FIC,
> the Root Port driver's inbound address translation may vary.
> 
> For all current supported designs and all future expected designs,
> inbound address translation done by a FIC on PolarFire SoC varies
> depending on whether PolarFire SoC in operating in dma-coherent mode or
> dma-noncoherent mode.
> 
> The setup of the outbound address translation tables in the root port
> driver only needs to handle these two cases.
> 
> Setup the inbound address translation tables to one of two address
> translations, depending on whether the rootport is marked as dma-coherent or
> dma-noncoherent.
> 
> Fixes: 6f15a9c9f941 ("PCI: microchip: Add Microchip Polarfire PCIe controller driver")
> Signed-off-by: Daire McNamara <daire.mcnamara@...rochip.com>

Acked-by: Conor Dooley <conor.dooley@...rochip.com>

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