linux-kernel - [PATCH] riscv: dts: starfive: add pcie1 on the star64

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Message-ID: <20240626-traverse-excitable-a1d9be38a9da@spud>
Date: Wed, 26 Jun 2024 21:00:57 +0100
From: Conor Dooley <conor@...nel.org>
To: linux-riscv@...ts.infradead.org
Cc: conor@...nel.org,
	Conor Dooley <conor.dooley@...rochip.com>,
	Minda Chen <minda.chen@...rfivetech.com>,
	Rob Herring <robh+dt@...nel.org>,
	devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org
Subject: [PATCH] riscv: dts: starfive: add pcie1 on the star64

From: Conor Dooley <conor.dooley@...rochip.com>

It was reported to me that the star64 actually /does/ have an exposed
PCIe port, despite the commit message there. In my original conversation
with Minda, they said that pcie1 was available there and pcie0 was not,
but the v2 patch didn't actually add pcie1 on the star64.

Signed-off-by: Conor Dooley <conor.dooley@...rochip.com>
---
I think I'll just squash this in and fixup the commit message, since the
patch is still at the top of my branch.

CC: Minda Chen <minda.chen@...rfivetech.com>
CC: Conor Dooley <conor@...nel.org>
CC: Rob Herring <robh+dt@...nel.org>,
CC: Emil Renner Berthing <emil.renner.berthing@...onical.com
CC: Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org
CC: devicetree@...r.kernel.org
CC: linux-kernel@...r.kernel.org
CC: linux-riscv@...ts.infradead.org
---
 arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts b/arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts
index 2d41f18e0359..b720cdd15ed6 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts
+++ b/arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts
@@ -39,6 +39,10 @@ phy1: ethernet-phy@1 {
 	};
 };
 
+&pcie1 {
+	status = "okay";
+};
+
 &phy0 {
 	rx-internal-delay-ps = <1900>;
 	tx-internal-delay-ps = <1500>;
-- 
2.43.0