linux-kernel - Re: [PATCH V2 00/13] Support Lunar Lake and Arrow Lake core PMU

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Message-ID: <CAP-5=fXvmDSPVOWhcNzSZ7icBh6PhdgpbopFCZgzZWYk_kGadA@mail.gmail.com>
Date: Tue, 25 Jun 2024 22:20:05 -0700
From: Ian Rogers <irogers@...gle.com>
To: kan.liang@...ux.intel.com
Cc: peterz@...radead.org, mingo@...nel.org, acme@...nel.org, 
	namhyung@...nel.org, adrian.hunter@...el.com, 
	alexander.shishkin@...ux.intel.com, linux-kernel@...r.kernel.org, 
	ak@...ux.intel.com, eranian@...gle.com
Subject: Re: [PATCH V2 00/13] Support Lunar Lake and Arrow Lake core PMU

On Tue, Jun 25, 2024 at 11:22 AM <kan.liang@...ux.intel.com> wrote:
>
> From: Kan Liang <kan.liang@...ux.intel.com>
>
> Changes since V1:
> - Add x86/intel_pmu_max_num_pebs/counters/counters_fixed()
> - Rename model-specific pebs_latency_data functions
> - Rename V6 counter MSRs
>
> From the core PMU' perspective, the Lunar Lake and Arrow Lake are the
> same, which are similar to the previous generation Meteor Lake. Both are
> hybrid platforms, with e-core and p-core.
>
> The key differences include:
> - The e-core supports 3 new fixed counters
> - The p-core supports an updated PEBS Data Source format
> - More GP counters (Updated event constraint table)
> - New Architectural performance monitoring V6
>   (New Perfmon MSRs aliasing, umask2, eq).
> - New PEBS format V6 (Counters Snapshotting group)
> - New RDPMC metrics clear mode
>
> The details for the above new features can be found in the Intel
> Architecture Instruction Set Extensions and Future Features (052).
> https://cdrdv2.intel.com/v1/dl/getContent/671368
>
> The counters may not be continuous anymore. Patch 1-2 converts the max
> number of counters to a mask of counters. The change is a generic change
> which impacts all X86 platforms.
>
> Patch 3-4 supports all the legacy features on LNL and ARL.
>
> Patch 5-7 supports the new Architectural performance monitoring V6.
>
> Patch 8-11 supports the new PEBS format V6.
>
> Patch 12 supports the new RDPMC metrics clear mode.
>
> Kan Liang (13):
>   perf/x86/intel: Support the PEBS event mask
>   perf/x86: Support counter mask
>   perf/x86: Add Lunar Lake and Arrow Lake support
>   perf/x86/intel: Rename model-specific pebs_latency_data functions
>   perf/x86/intel: Support new data source for Lunar Lake
>   perf/x86: Add config_mask to represent EVENTSEL bitmask
>   perf/x86/intel: Support PERFEVTSEL extension
>   perf/x86/intel: Support Perfmon MSRs aliasing
>   perf/x86: Extend event update interface
>   perf: Extend perf_output_read
>   perf/x86/intel: Move PEBS event update after the sample output
>   perf/x86/intel: Support PEBS counters snapshotting
>   perf/x86/intel: Support RDPMC metrics clear mode

Fwiw and beside the nit:

Reviewed-by: Ian Rogers <irogers@...gle.com>

It seems some of the behaviors could have tests upon them, would it be
possible to add them skipping the test on older and non-Intel
architectures?

Thanks,
Ian

>  arch/x86/events/amd/core.c           |  26 +-
>  arch/x86/events/core.c               | 123 +++----
>  arch/x86/events/intel/core.c         | 471 ++++++++++++++++++++-------
>  arch/x86/events/intel/ds.c           | 288 +++++++++++++---
>  arch/x86/events/intel/knc.c          |   2 +-
>  arch/x86/events/intel/p4.c           |  12 +-
>  arch/x86/events/intel/p6.c           |   2 +-
>  arch/x86/events/perf_event.h         | 105 +++++-
>  arch/x86/events/perf_event_flags.h   |   2 +-
>  arch/x86/events/zhaoxin/core.c       |  14 +-
>  arch/x86/include/asm/intel_ds.h      |   1 +
>  arch/x86/include/asm/msr-index.h     |   6 +
>  arch/x86/include/asm/perf_event.h    |  27 ++
>  include/uapi/linux/perf_event.h      |   6 +-
>  kernel/events/core.c                 |  15 +-
>  tools/perf/Documentation/topdown.txt |   9 +-
>  16 files changed, 839 insertions(+), 270 deletions(-)
>
> --
> 2.35.1
>