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Message-ID: <20240626-qps615-v1-0-2ade7bd91e02@quicinc.com>
Date: Wed, 26 Jun 2024 18:07:48 +0530
From: Krishna chaitanya chundru <quic_krichai@...cinc.com>
To: Bartosz Golaszewski <brgl@...ev.pl>,
Manivannan Sadhasivam
<manivannan.sadhasivam@...aro.org>,
Lorenzo Pieralisi
<lpieralisi@...nel.org>,
Krzysztof WilczyĆski
<kw@...ux.com>,
Rob Herring <robh@...nel.org>, Bjorn Helgaas
<bhelgaas@...gle.com>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley
<conor+dt@...nel.org>,
Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio
<konrad.dybcio@...aro.org>,
Jingoo Han <jingoohan1@...il.com>
CC: <quic_vbadigan@...cinc.com>, <quic_skananth@...cinc.com>,
<quic_nitegupt@...cinc.com>, <linux-arm-msm@...r.kernel.org>,
<linux-pci@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>,
Krishna chaitanya chundru
<quic_krichai@...cinc.com>
Subject: [PATCH RFC 0/7] PCI: enable Power and configure the QPS615 PCIe
switch
QPS615 is the PCIe switch which has one upstream and three downstream
ports. One of the downstream ports is used as endpoint device of Ethernet
MAC. Other two downstream ports are supposed to connect to external
device. One Host can connect to QPS615 by upstream port.
QPS615 switch power is controlled by the GPIO's. After powering on
the switch will immediately participate in the link training. if the
host is also ready by that time PCIe link will established.
The QPS615 needs to configured certain parameters like de-emphasis,
disable unused port etc before link is established. These settings
vary from platform to platform.
As the controller starts link training before the probe of pwrctl driver,
the PCIe link may come up before configuring the switch itself.
To avoid this introduce two functions in pci_ops to start_link() &
stop_link() which will disable the link training if the PCIe link is
not up yet.
Now PCI pwrctl device is the child of the pci-pcie bridge, if we want
to enable the suspend resume for pwrctl device there may be issues
since pci bridge will try to access some registers in the config which
may cause timeouts or Un clocked access as the power can be removed in
the suspend of pwrctl driver.
To solve this make PCIe controller as parent to the pci pwr ctrl driver
and create devlink between host bridge and pci pwrctl driver so that
pci pwrctl driver will go suspend only after all the PCIe devices went
to suspend.
In pci pwrctl driver use stop_link() to keep the link in D3cold and
start_link() to bring back link to D0.
This series is developed on top the series:
https://lore.kernel.org/lkml/20240612082019.19161-1-brgl@bgdev.pl/
we are sending this series to get coments on the usage of stop_link
and start_link which is being add in this series.
Signed-off-by: Krishna chaitanya chundru <quic_krichai@...cinc.com>
---
Krishna chaitanya chundru (7):
dt: bindings: add qcom,qps615.yaml
arm64: dts: qcom: qcs6490-rb3gen2: Add qps615 node
pci: Change the parent of the platform devices for child OF nodes
pci: Add new start_link() & stop_link function ops
pci: dwc: Add support for new pci function op
pci: qcom: Add support for start_link() & stop_link()
pci: pwrctl: Add power control driver for qps615
.../devicetree/bindings/pci/qcom,qps615.yaml | 73 ++++++
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 55 ++++
drivers/pci/bus.c | 5 +-
drivers/pci/controller/dwc/pcie-designware-host.c | 19 ++
drivers/pci/controller/dwc/pcie-qcom.c | 108 +++++++-
drivers/pci/pwrctl/Kconfig | 7 +
drivers/pci/pwrctl/Makefile | 1 +
drivers/pci/pwrctl/core.c | 7 +-
drivers/pci/pwrctl/pci-pwrctl-qps615.c | 278 +++++++++++++++++++++
include/linux/pci.h | 2 +
10 files changed, 541 insertions(+), 14 deletions(-)
---
base-commit: d737627471e5b3962eedae870aa0475d6c9bba18
change-id: 20240624-qps615-faa0cc60dc74
Best regards,
--
Krishna chaitanya chundru <quic_krichai@...cinc.com>
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