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Message-ID: <20240628220014.GB2213719@rocinante>
Date: Sat, 29 Jun 2024 07:00:14 +0900
From: Krzysztof WilczyĆski <kw@...ux.com>
To: Jan Kiszka <jan.kiszka@...mens.com>
Cc: Lorenzo Pieralisi <lpieralisi@...nel.org>,
Rob Herring <robh@...nel.org>, Bjorn Helgaas <bhelgaas@...gle.com>,
Kishon Vijay Abraham I <kishon@...nel.org>,
Siddharth Vadapalli <s-vadapalli@...com>,
Vignesh Raghavendra <vigneshr@...com>, Nishanth Menon <nm@...com>,
"linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
linux-arm-kernel <linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH v5] PCI: keystone: Add workaround for Errata #i2037
(AM65x SR 1.0)
Hello,
> Errata #i2037 in AM65x/DRA80xM Processors Silicon Revision 1.0
> (SPRZ452D_July 2018_Revised December 2019 [1]) mentions when an
> inbound PCIe TLP spans more than two internal AXI 128-byte bursts,
> the bus may corrupt the packet payload and the corrupt data may
> cause associated applications or the processor to hang.
>
> The workaround for Errata #i2037 is to limit the maximum read
> request size and maximum payload size to 128 bytes. Add workaround
> for Errata #i2037 here. The errata and workaround is applicable
> only to AM65x SR 1.0 and later versions of the silicon will have
> this fixed.
>
> [1] -> https://www.ti.com/lit/er/sprz452i/sprz452i.pdf
Applied to controller/keystone, thank you!
[1/1] PCI: keystone: Add workaround for Errata #i2037 (AM65x SR 1.0)
https://git.kernel.org/pci/pci/c/86f271f22bbb
Krzysztof
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