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Date: Sat, 29 Jun 2024 07:28:31 +0530
From: Akhil P Oommen <quic_akhilpo@...cinc.com>
To: Rob Clark <robdclark@...il.com>
CC: <dri-devel@...ts.freedesktop.org>, <linux-arm-msm@...r.kernel.org>,
<freedreno@...ts.freedesktop.org>, Rob Clark <robdclark@...omium.org>,
"Dmitry Baryshkov" <dmitry.baryshkov@...aro.org>,
Konrad Dybcio
<konrad.dybcio@...aro.org>, Sean Paul <sean@...rly.run>,
Abhinav Kumar
<quic_abhinavk@...cinc.com>,
Marijn Suijten <marijn.suijten@...ainline.org>,
David Airlie <airlied@...il.com>, Daniel Vetter <daniel@...ll.ch>,
open list
<linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v4 1/5] drm/msm/adreno: Split up giant device table
On Tue, Jun 18, 2024 at 09:42:47AM -0700, Rob Clark wrote:
> From: Rob Clark <robdclark@...omium.org>
>
> Split into a separate table per generation, in preparation to move each
> gen's device table to it's own file.
>
> Signed-off-by: Rob Clark <robdclark@...omium.org>
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@...aro.org>
> ---
> drivers/gpu/drm/msm/adreno/adreno_device.c | 67 +++++++++++++++++-----
> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 10 ++++
> 2 files changed, 63 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
> index c3703a51287b..a57659eaddc2 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_device.c
> +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
> @@ -20,7 +20,7 @@ bool allow_vram_carveout = false;
> MODULE_PARM_DESC(allow_vram_carveout, "Allow using VRAM Carveout, in place of IOMMU");
> module_param_named(allow_vram_carveout, allow_vram_carveout, bool, 0600);
>
> -static const struct adreno_info gpulist[] = {
> +static const struct adreno_info a2xx_gpus[] = {
> {
> .chip_ids = ADRENO_CHIP_IDS(0x02000000),
> .family = ADRENO_2XX_GEN1,
> @@ -54,7 +54,12 @@ static const struct adreno_info gpulist[] = {
> .gmem = SZ_512K,
> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> .init = a2xx_gpu_init,
> - }, {
> + }
> +};
> +DECLARE_ADRENO_GPULIST(a2xx);
> +
> +static const struct adreno_info a3xx_gpus[] = {
> + {
> .chip_ids = ADRENO_CHIP_IDS(0x03000512),
> .family = ADRENO_3XX,
> .fw = {
> @@ -116,7 +121,12 @@ static const struct adreno_info gpulist[] = {
> .gmem = SZ_1M,
> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> .init = a3xx_gpu_init,
> - }, {
> + }
> +};
> +DECLARE_ADRENO_GPULIST(a3xx);
> +
> +static const struct adreno_info a4xx_gpus[] = {
> + {
> .chip_ids = ADRENO_CHIP_IDS(0x04000500),
> .family = ADRENO_4XX,
> .revn = 405,
> @@ -149,7 +159,12 @@ static const struct adreno_info gpulist[] = {
> .gmem = (SZ_1M + SZ_512K),
> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> .init = a4xx_gpu_init,
> - }, {
> + }
> +};
> +DECLARE_ADRENO_GPULIST(a4xx);
> +
> +static const struct adreno_info a5xx_gpus[] = {
> + {
> .chip_ids = ADRENO_CHIP_IDS(0x05000600),
> .family = ADRENO_5XX,
> .revn = 506,
> @@ -274,7 +289,12 @@ static const struct adreno_info gpulist[] = {
> .quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE,
> .init = a5xx_gpu_init,
> .zapfw = "a540_zap.mdt",
> - }, {
> + }
> +};
> +DECLARE_ADRENO_GPULIST(a5xx);
> +
> +static const struct adreno_info a6xx_gpus[] = {
> + {
> .chip_ids = ADRENO_CHIP_IDS(0x06010000),
> .family = ADRENO_6XX_GEN1,
> .revn = 610,
> @@ -520,7 +540,12 @@ static const struct adreno_info gpulist[] = {
> .zapfw = "a690_zap.mdt",
> .hwcg = a690_hwcg,
> .address_space_size = SZ_16G,
> - }, {
> + }
> +};
> +DECLARE_ADRENO_GPULIST(a6xx);
> +
> +static const struct adreno_info a7xx_gpus[] = {
> + {
> .chip_ids = ADRENO_CHIP_IDS(0x07000200),
> .family = ADRENO_6XX_GEN1, /* NOT a mistake! */
> .fw = {
> @@ -582,7 +607,17 @@ static const struct adreno_info gpulist[] = {
> .init = a6xx_gpu_init,
> .zapfw = "gen70900_zap.mbn",
> .address_space_size = SZ_16G,
> - },
> + }
> +};
> +DECLARE_ADRENO_GPULIST(a7xx);
> +
> +static const struct adreno_gpulist *gpulists[] = {
> + &a2xx_gpulist,
> + &a3xx_gpulist,
> + &a4xx_gpulist,
> + &a5xx_gpulist,
> + &a6xx_gpulist,
> + &a6xx_gpulist,
Typo. a6xx_gpulist -> a7xx_gpulist.
-Akhil
> };
>
> MODULE_FIRMWARE("qcom/a300_pm4.fw");
> @@ -617,13 +652,17 @@ MODULE_FIRMWARE("qcom/yamato_pm4.fw");
> static const struct adreno_info *adreno_info(uint32_t chip_id)
> {
> /* identify gpu: */
> - for (int i = 0; i < ARRAY_SIZE(gpulist); i++) {
> - const struct adreno_info *info = &gpulist[i];
> - if (info->machine && !of_machine_is_compatible(info->machine))
> - continue;
> - for (int j = 0; info->chip_ids[j]; j++)
> - if (info->chip_ids[j] == chip_id)
> - return info;
> + for (int i = 0; i < ARRAY_SIZE(gpulists); i++) {
> + for (int j = 0; j < gpulists[i]->gpus_count; j++) {
> + const struct adreno_info *info = &gpulists[i]->gpus[j];
> +
> + if (info->machine && !of_machine_is_compatible(info->machine))
> + continue;
> +
> + for (int k = 0; info->chip_ids[k]; k++)
> + if (info->chip_ids[k] == chip_id)
> + return info;
> + }
> }
>
> return NULL;
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> index 77526892eb8c..17aba8c58f3d 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> @@ -114,6 +114,16 @@ struct adreno_info {
>
> #define ADRENO_CHIP_IDS(tbl...) (uint32_t[]) { tbl, 0 }
>
> +struct adreno_gpulist {
> + const struct adreno_info *gpus;
> + unsigned gpus_count;
> +};
> +
> +#define DECLARE_ADRENO_GPULIST(name) \
> +const struct adreno_gpulist name ## _gpulist = { \
> + name ## _gpus, ARRAY_SIZE(name ## _gpus) \
> +}
> +
> /*
> * Helper to build a speedbin table, ie. the table:
> * fuse | speedbin
> --
> 2.45.2
>
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