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Message-ID: <ccb669ad-be56-4dbd-ad9c-851a94b933eb@sifive.com>
Date: Mon, 1 Jul 2024 10:13:50 -0500
From: Samuel Holland <samuel.holland@...ive.com>
To: Jesse Taube <jesse@...osinc.com>
Cc: Jonathan Corbet <corbet@....net>, Paul Walmsley
<paul.walmsley@...ive.com>, Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>, Conor Dooley <conor@...nel.org>,
Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Clément Léger <cleger@...osinc.com>,
Evan Green <evan@...osinc.com>, Andrew Jones <ajones@...tanamicro.com>,
Charlie Jenkins <charlie@...osinc.com>, Xiao Wang <xiao.w.wang@...el.com>,
Andy Chiu <andy.chiu@...ive.com>, Eric Biggers <ebiggers@...gle.com>,
Greentime Hu <greentime.hu@...ive.com>, Björn Töpel
<bjorn@...osinc.com>, Heiko Stuebner <heiko@...ech.de>,
Costa Shulyupin <costa.shul@...hat.com>,
Andrew Morton <akpm@...ux-foundation.org>, Baoquan He <bhe@...hat.com>,
Anup Patel <apatel@...tanamicro.com>, Zong Li <zong.li@...ive.com>,
Sami Tolvanen <samitolvanen@...gle.com>,
Ben Dooks <ben.dooks@...ethink.co.uk>,
Alexandre Ghiti <alexghiti@...osinc.com>,
"Gustavo A. R. Silva" <gustavoars@...nel.org>,
Erick Archer <erick.archer@....com>, Joel Granados <j.granados@...sung.com>,
linux-doc@...r.kernel.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org, linux-riscv@...ts.infradead.org
Subject: Re: [PATCH v3 6/8] RISC-V: Detect unaligned vector accesses supported
Hi Jesse,
On 2024-06-24 7:49 PM, Jesse Taube wrote:
> Run a unaligned vector access to test if the system supports
> vector unaligned access. Add the result to a new key in hwprobe.
> This is useful for usermode to know if vector misaligned accesses are
> supported and if they are faster or slower than equivalent byte accesses.
>
> Signed-off-by: Jesse Taube <jesse@...osinc.com>
> V1 -> V2:
You are missing the "---" here, so the changelog is leaking into the commit message.
> - Add Kconfig options
> - Add insn_is_vector
> - Add handle_vector_misaligned_load
> - Fix build
> - Seperate vector from scalar misaligned access
> - This patch was almost completely rewritten
> V2 -> V3:
> - Fixed CONFIG_ in Kconfig
> - Fixed check_vector_unaligned_access_emulated leaving
> vector_misaligned_access as unknown.
> - Remove local_irq_enable
> - Remove RISCV_DETECT_VECTOR_UNALIGNED_ACCESS
> - Remove RISCV_VEC_UNALIGNED_ACCESS_UNSUPPORTED
> ---
> arch/riscv/Kconfig | 35 ++++++
> arch/riscv/include/asm/cpufeature.h | 5 +
> arch/riscv/include/asm/entry-common.h | 11 --
> arch/riscv/include/asm/hwprobe.h | 2 +-
> arch/riscv/include/asm/vector.h | 1 +
> arch/riscv/include/uapi/asm/hwprobe.h | 5 +
> arch/riscv/kernel/Makefile | 4 +-
> arch/riscv/kernel/sys_hwprobe.c | 35 ++++++
> arch/riscv/kernel/traps_misaligned.c | 120 ++++++++++++++++++++-
> arch/riscv/kernel/unaligned_access_speed.c | 9 +-
> arch/riscv/kernel/vector.c | 2 +-
> 11 files changed, 209 insertions(+), 20 deletions(-)
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index 34d24242e37a..ffbe0fdd7fb3 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -717,12 +717,26 @@ config THREAD_SIZE_ORDER
> Specify the Pages of thread stack size (from 4KB to 64KB), which also
> affects irq stack size, which is equal to thread stack size.
>
> +config RISCV_MISALIGNED
> + bool
> + help
> + Embed support for detecting and emulating misaligned
> + scalar or vector loads and stores.
> +
> config RISCV_SCALAR_MISALIGNED
> bool
> + select RISCV_MISALIGNED
> select SYSCTL_ARCH_UNALIGN_ALLOW
> help
> Embed support for emulating misaligned loads and stores.
>
> +config RISCV_VECTOR_MISALIGNED
> + bool
> + select RISCV_MISALIGNED
> + depends on RISCV_ISA_V
> + help
> + Enable detecting support for vector misaligned loads and stores.
> +
> choice
> prompt "Unaligned Accesses Support"
> default RISCV_PROBE_UNALIGNED_ACCESS
> @@ -774,6 +788,27 @@ config RISCV_EFFICIENT_UNALIGNED_ACCESS
>
> endchoice
>
> +choice
> + prompt "Vector unaligned Accesses Support"
> + depends on RISCV_ISA_V
> + default RISCV_PROBE_VECTOR_UNALIGNED_ACCESS
> + help
> + This determines the level of support for vector unaligned accesses. This
> + information is used by the kernel to perform optimizations. It is also
> + exposed to user space via the hwprobe syscall. The hardware will be
> + probed at boot by default.
> +
> +config RISCV_PROBE_VECTOR_UNALIGNED_ACCESS
> + bool "Probe speed of vector unaligned accesses"
> + select RISCV_VECTOR_MISALIGNED
> + help
> + During boot, the kernel will run a series of tests to determine the
> + speed of vector unaligned accesses if they are supported. This probing
> + will dynamically determine the speed of vector unaligned accesses on
> + the underlying system if they are supported.
> +
> +endchoice
> +
> endmenu # "Platform type"
>
> menu "Kernel features"
> diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h
> index 0ed7d99c14dd..f25f56f9bfaa 100644
> --- a/arch/riscv/include/asm/cpufeature.h
> +++ b/arch/riscv/include/asm/cpufeature.h
> @@ -45,6 +45,11 @@ static inline bool unaligned_ctl_available(void)
> }
> #endif
>
> +bool check_vector_unaligned_access_emulated_all_cpus(void);
> +#if defined(CONFIG_RISCV_VECTOR_MISALIGNED)
> +DECLARE_PER_CPU(long, vector_misaligned_access);
> +#endif
> +
> #if defined(CONFIG_RISCV_PROBE_UNALIGNED_ACCESS)
> DECLARE_STATIC_KEY_FALSE(fast_unaligned_access_speed_key);
>
> diff --git a/arch/riscv/include/asm/entry-common.h b/arch/riscv/include/asm/entry-common.h
> index 0a4e3544c877..7b32d2b08bb6 100644
> --- a/arch/riscv/include/asm/entry-common.h
> +++ b/arch/riscv/include/asm/entry-common.h
> @@ -25,18 +25,7 @@ static inline void arch_exit_to_user_mode_prepare(struct pt_regs *regs,
> void handle_page_fault(struct pt_regs *regs);
> void handle_break(struct pt_regs *regs);
>
> -#ifdef CONFIG_RISCV_SCALAR_MISALIGNED
> int handle_misaligned_load(struct pt_regs *regs);
> int handle_misaligned_store(struct pt_regs *regs);
> -#else
> -static inline int handle_misaligned_load(struct pt_regs *regs)
> -{
> - return -1;
> -}
> -static inline int handle_misaligned_store(struct pt_regs *regs)
> -{
> - return -1;
> -}
> -#endif
>
> #endif /* _ASM_RISCV_ENTRY_COMMON_H */
> diff --git a/arch/riscv/include/asm/hwprobe.h b/arch/riscv/include/asm/hwprobe.h
> index 150a9877b0af..ef01c182af2b 100644
> --- a/arch/riscv/include/asm/hwprobe.h
> +++ b/arch/riscv/include/asm/hwprobe.h
> @@ -8,7 +8,7 @@
>
> #include <uapi/asm/hwprobe.h>
>
> -#define RISCV_HWPROBE_MAX_KEY 7
> +#define RISCV_HWPROBE_MAX_KEY 8
>
> static inline bool riscv_hwprobe_key_is_valid(__s64 key)
> {
> diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h
> index be7d309cca8a..99b0f91db9ee 100644
> --- a/arch/riscv/include/asm/vector.h
> +++ b/arch/riscv/include/asm/vector.h
> @@ -21,6 +21,7 @@
>
> extern unsigned long riscv_v_vsize;
> int riscv_v_setup_vsize(void);
> +bool insn_is_vector(u32 insn_buf);
> bool riscv_v_first_use_handler(struct pt_regs *regs);
> void kernel_vector_begin(void);
> void kernel_vector_end(void);
> diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
> index 023b7771d1b7..2fee870e41bb 100644
> --- a/arch/riscv/include/uapi/asm/hwprobe.h
> +++ b/arch/riscv/include/uapi/asm/hwprobe.h
> @@ -75,6 +75,11 @@ struct riscv_hwprobe {
> #define RISCV_HWPROBE_MISALIGNED_MASK (7 << 0)
> #define RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE 6
> #define RISCV_HWPROBE_KEY_MISALIGNED_PERF 7
> +#define RISCV_HWPROBE_KEY_VEC_MISALIGNED_PERF 8
> +#define RISCV_HWPROBE_VEC_MISALIGNED_UNKNOWN 0
> +#define RISCV_HWPROBE_VEC_MISALIGNED_SLOW 2
> +#define RISCV_HWPROBE_VEC_MISALIGNED_FAST 3
> +#define RISCV_HWPROBE_VEC_MISALIGNED_UNSUPPORTED 4
We are spelling out "SCALAR" in the fixes series here[1], so for consistency we
should spell out "VECTOR" as well.
Regards,
Samuel
[1]: https://lore.kernel.org/linux-riscv/20240627172238.2460840-2-evan@rivosinc.com/
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