linux-kernel - Re: [PATCH v6 5/5] x86/gsseg: use the LKGS instruction if available for load_gs

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Message-ID: <20240701094757.GCZoJ7TWGdv2Cm6egY@fat_crate.local>
Date: Mon, 1 Jul 2024 11:47:57 +0200
From: Borislav Petkov <bp@...en8.de>
To: "H. Peter Anvin" <hpa@...or.com>
Cc: Xin Li <xin3.li@...el.com>, linux-kernel@...r.kernel.org,
	x86@...nel.org, tglx@...utronix.de, mingo@...hat.com,
	dave.hansen@...ux.intel.com, peterz@...radead.org,
	brgerst@...il.com, chang.seok.bae@...el.com, jgross@...e.com
Subject: Re: [PATCH v6 5/5] x86/gsseg: use the LKGS instruction if available
 for load_gs_index()

On Mon, Jul 01, 2024 at 01:01:54AM -0700, H. Peter Anvin wrote:
> I don't know. It is stated in a number of places, but I don't know if it is
> explicit in *this* specific context.

Right, so the *read* side is explained tho, in both manuals and I presume for
the other direction it is implied that the 16 LSBits are used:

AMD:

"When reading segment-registers with a 32-bit operand size, the processor
zero-extends the 16-bit selector results to 32 bits. When reading
segment-registers with a 64-bit operand size, the processor zero-extends the
16-bit selector to 64 bits."

Intel:

"When executing MOV Reg, Sreg, the processor copies the content of Sreg to the
16 least significant bits of the general-purpose register. The upper bits of
the destination register are zero for most IA-32 processors (Pentium Pro
processors and later) and all Intel 64 processors, with the exception that
bits 31:16 are undefined for Intel Quark X1000 processors, Pentium, and
earlier processors."

-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette