linux-kernel - Re: [PATCH v3 03/13] riscv: dts: allwinner: Add xtheadvector to the D1/D1s devicetree

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20240702-protegee-exploring-49c0dbd831e5@spud>
Date: Tue, 2 Jul 2024 16:39:26 +0100
From: Conor Dooley <conor@...nel.org>
To: Yu-Chien Peter Lin <peterlin@...estech.com>
Cc: Samuel Holland <samuel.holland@...ive.com>,
	Charlie Jenkins <charlie@...osinc.com>,
	linux-riscv@...ts.infradead.org, devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org, linux-sunxi@...ts.linux.dev,
	linux-doc@...r.kernel.org, linux-kselftest@...r.kernel.org,
	Conor Dooley <conor.dooley@...rochip.com>,
	Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Paul Walmsley <paul.walmsley@...ive.com>,
	Palmer Dabbelt <palmer@...belt.com>,
	Albert Ou <aou@...s.berkeley.edu>,
	Jisheng Zhang <jszhang@...nel.org>, Chen-Yu Tsai <wens@...e.org>,
	Jernej Skrabec <jernej.skrabec@...il.com>,
	Samuel Holland <samuel@...lland.org>,
	Jonathan Corbet <corbet@....net>, Shuah Khan <shuah@...nel.org>,
	Guo Ren <guoren@...nel.org>, Evan Green <evan@...osinc.com>,
	Andy Chiu <andy.chiu@...ive.com>,
	Jessica Clarke <jrtc27@...c27.com>, tim609@...estech.com,
	dminus@...estech.com, ycliang@...estech.com
Subject: Re: [PATCH v3 03/13] riscv: dts: allwinner: Add xtheadvector to the
 D1/D1s devicetree

On Tue, Jul 02, 2024 at 05:46:42PM +0800, Yu-Chien Peter Lin wrote:
> On Mon, Jul 01, 2024 at 05:31:01PM +0100, Conor Dooley wrote:
> > On Mon, Jul 01, 2024 at 11:11:55AM -0500, Samuel Holland wrote:
> > > Hi Conor, Charlie,
> > > 
> > > On 2024-07-01 11:07 AM, Conor Dooley wrote:
> > > > On Mon, Jul 01, 2024 at 10:27:01AM -0500, Samuel Holland wrote:
> > > >> On 2024-06-19 6:57 PM, Charlie Jenkins wrote:
> > > >>> diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
> > > >>> index 64c3c2e6cbe0..6367112e614a 100644
> > > >>> --- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
> > > >>> +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
> > > >>> @@ -27,7 +27,8 @@ cpu0: cpu@0 {
> > > >>>  			riscv,isa = "rv64imafdc";
> > > >>
> > > >> The ISA string should be updated to keep it in sync with riscv,isa-extensions.
> > > > 
> > > > This probably looks like this cos I said that the kernel shouldn't parse
> > > > vendor extensions from "riscv,isa". My rationale was that we have
> > > > basically no control of what a vendor extension means in riscv,isa so 
> > > > we shouldn't parse them from it (so marginally worse than standard
> > > > extensions, where it means what the spec says except when it doesn't).
> > > > 
> > > > Given how we implement the parsing, it also meant we weren't implying
> > > > meanings for vendor extensions ACPI-land, where we also can't ensure the
> > > > meanings or that they remain stable. That change is in a different
> > > > series:
> > > > https://patchwork.kernel.org/project/linux-riscv/patch/20240609-support_vendor_extensions-v2-1-9a43f1fdcbb9@rivosinc.com/
> > > > 
> > > > Although now that I think about it, this might break xandespmu... I
> > > > dunno if the Andes guys switched over to using the new property outside
> > > > of the single dts in the kernel tree using their SoC. We could
> > > > potentially special-case that extension if they haven't - but my
> > > > position on this mostly is that if you want to use vendor extensions you
> > > > should not be using riscv,isa (even if the regex doesn't complain if you
> > > > add them). I'd like to leave the code in the other patch as-is if we can
> > > > help it.
> > > > 
> > > > I added Yu Chien Peter Lin here, maybe they can let us know what they're
> > > > doing.
> > > 
> > > OK, that makes sense to me. Then please ignore my original comment.
> > 
> > Should the xandespmu thing be an issue, I'd suggest we just do something
> > like the following, in place of the new switch arm added by Charlie:
> > 
> > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> > index ec4bff7a827c..bb99b4055ec2 100644
> > --- a/arch/riscv/kernel/cpufeature.c
> > +++ b/arch/riscv/kernel/cpufeature.c
> > @@ -628,6 +628,17 @@ static void __init riscv_parse_isa_string(const char *isa, unsigned long *bitmap
> >  		if (unlikely(ext_err))
> >  			continue;
> >  
> > +		if (*ext == 'x' && acpi_disabled) {
> > +			/*
> > +			 * xandespmu predates this "rule", so special case it for
> > +			 * hysterical raisins
> > +			 */
> > +			if (strncasecmp(ext, "xandespmu", ext_end - ext)) {
> > +				pr_warn_once("Vendor extensions are ignored in riscv,isa. Use riscv,isa-extensions instead.");
> > +				break;
> > +			}
> > +		}
> > +
> >  		match_isa_ext(ext, ext_end, bitmap);
> >  	}
> >  }
> > 
> 
> Thanks for the hands-up!
> We don't use the deprecated riscv,isa to specify xandespmu, so no
> need to address this special case.

Great, that's good to know - thanks!

Download attachment "signature.asc" of type "application/pgp-signature" (229 bytes)