linux-kernel - Re: [PATCH v3 3/9] pinctrl: renesas: rzg2l: Support output enable on RZ/G2L

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Message-ID: <CAMuHMdWbq_L1o3WxeHoD4n12DjEYV_k9RzGQbYP1EzhX6tr6_A@mail.gmail.com>
Date: Thu, 4 Jul 2024 19:29:32 +0200
From: Geert Uytterhoeven <geert@...ux-m68k.org>
To: Paul Barker <paul.barker.ct@...renesas.com>
Cc: Magnus Damm <magnus.damm@...il.com>, Rob Herring <robh@...nel.org>, 
	Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, 
	Linus Walleij <linus.walleij@...aro.org>, 
	Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>, linux-renesas-soc@...r.kernel.org, 
	devicetree@...r.kernel.org, linux-gpio@...r.kernel.org, 
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH v3 3/9] pinctrl: renesas: rzg2l: Support output enable on RZ/G2L

Hi Paul,

On Tue, Jun 25, 2024 at 10:03 PM Paul Barker
<paul.barker.ct@...renesas.com> wrote:
> On the RZ/G2L SoC family, the direction of the Ethernet TXC/TX_CLK
> signal is selectable to support an Ethernet PHY operating in either MII
> or RGMII mode. By default, the signal is configured as an input and MII
> mode is supported. The ETH_MODE register can be modified to configure
> this signal as an output to support RGMII mode.
>
> As this signal is by default an input, and can optionally be switched to
> an output, it maps neatly onto an `output-enable` property in the device
> tree.
>
> Signed-off-by: Paul Barker <paul.barker.ct@...renesas.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@...der.be>
> Acked-by: Linus Walleij <linus.walleij@...aro.org>
> ---
> Changes v2->v3:
>   * Picked up Linus W's Acked-by tag & Geert's Reviewed-by tag.
>   * Simplify arguments to rzg2l_pin_to_oen_bit() and decode pin/caps
>     inside this function. No check is needed for dedicated pins as no
>     dedicated pins support OEN in the RZ/G2L family.

Thanks for the update!

> --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> @@ -994,6 +994,61 @@ static bool rzg2l_ds_is_supported(struct rzg2l_pinctrl *pctrl, u32 caps,
>         return false;
>  }
>
> +static int rzg2l_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin)
> +{
> +       u64 *pin_data = pctrl->desc.pins[_pin].drv_data;
> +       u64 caps = FIELD_GET(PIN_CFG_MASK, *pin_data);
> +       u8 max_pin = pctrl->data->hwcfg->oen_max_pin;
> +       u8 pin = RZG2L_PIN_ID_TO_PIN(_pin);
> +
> +       if (pin > max_pin)

Likewise 2/9, just use the original directly.
No need to resend, I can do this while applying.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds