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Message-ID: <236cfab6-6f5a-43c3-98f2-43a8d66af60c@oss.nxp.com>
Date: Thu, 4 Jul 2024 16:25:09 +0300
From: Ciprian Marian Costea <ciprianmarian.costea@....nxp.com>
To: Fabio Estevam <festevam@...il.com>
Cc: Chester Lin <chester62515@...il.com>, Matthias Brugger
 <mbrugger@...e.com>, Ghennadi Procopciuc <ghennadi.procopciuc@....nxp.com>,
 Shawn Guo <shawnguo@...nel.org>, Sascha Hauer <s.hauer@...gutronix.de>,
 Pengutronix Kernel Team <kernel@...gutronix.de>,
 Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
 Conor Dooley <conor+dt@...nel.org>, linux-arm-kernel@...ts.infradead.org,
 imx@...ts.linux.dev, devicetree@...r.kernel.org,
 linux-kernel@...r.kernel.org, s32@....com
Subject: Re: [PATCH] arm64: dts: s32g: Disable usdhc write-protect

On 7/4/2024 4:13 PM, Fabio Estevam wrote:
> Hi Ciprian,
> 
> On Thu, Jul 4, 2024 at 9:03 AM Ciprian Costea
> <ciprianmarian.costea@....nxp.com> wrote:
> 
>> --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
>> +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
>> @@ -145,6 +145,7 @@ usdhc0: mmc@...f0000 {
>>                          clocks = <&clks 32>, <&clks 31>, <&clks 33>;
>>                          clock-names = "ipg", "ahb", "per";
>>                          bus-width = <8>;
>> +                       disable-wp;
> 
> This should be better placed on the board dts instead of describing it
> in the SoC dtsi.
> 
> Some boards may use a GPIO to describe the write protect pin via the
> 'wp-gpios' property.

Hello Fabio,

Thanks for your suggestion. I will update accordingly in version 2 of 
this patch.

Best Regards,
Ciprian

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