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Message-ID: <ed3f2b70-fc71-4bde-b4d6-c9ad4bb0f715@suse.de>
Date: Thu, 4 Jul 2024 16:51:31 +0300
From: Stanimir Varbanov <svarbanov@...e.de>
To: Jim Quinlan <james.quinlan@...adcom.com>, linux-pci@...r.kernel.org,
Nicolas Saenz Julienne <nsaenz@...nel.org>,
Bjorn Helgaas <bhelgaas@...gle.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
Cyril Brulebois <kibi@...ian.org>, Stanimir Varbanov <svarbanov@...e.de>,
bcm-kernel-feedback-list@...adcom.com, jim2101024@...il.com
Cc: Florian Fainelli <florian.fainelli@...adcom.com>,
Lorenzo Pieralisi <lpieralisi@...nel.org>,
Krzysztof WilczyĆski <kw@...ux.com>,
Rob Herring <robh@...nel.org>,
"moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE"
<linux-rpi-kernel@...ts.infradead.org>,
"moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE"
<linux-arm-kernel@...ts.infradead.org>,
open list <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v2 11/12] PCI: brcmstb: Enable 7712 SOCs
Hi Jim,
On 7/3/24 21:02, Jim Quinlan wrote:
> The Broadcom STB 7712 is the sibling chip of the RPi 5 (2712).
>
> Signed-off-by: Jim Quinlan <james.quinlan@...adcom.com>
> ---
> drivers/pci/controller/pcie-brcmstb.c | 19 ++++++++++++++++++-
> 1 file changed, 18 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
> index 1c3ce0c182d1..39d7dea282ff 100644
> --- a/drivers/pci/controller/pcie-brcmstb.c
> +++ b/drivers/pci/controller/pcie-brcmstb.c
> @@ -1216,7 +1216,9 @@ static void brcm_config_clkreq(struct brcm_pcie *pcie)
> * atypical and should happen only with older devices.
> */
> clkreq_cntl |= PCIE_MISC_HARD_PCIE_HARD_DEBUG_L1SS_ENABLE_MASK;
> - brcm_extend_rbus_timeout(pcie);
> + /* 7712 does not have this (RGR1) timer */
> + if (pcie->type != BCM7712)
> + brcm_extend_rbus_timeout(pcie);
I'd move the check in brcm_extend_rbus_timeout() function.
Otherwise:
Reviewed-by: Stanimir Varbanov <svarbanov@...e.de>
>
> } else {
> /*
> @@ -1628,6 +1630,13 @@ static const int pcie_offsets_bmips_7425[] = {
> [PCIE_INTR2_CPU_BASE] = 0x4300,
> };
>
> +static const int pcie_offset_bcm7712[] = {
> + [EXT_CFG_INDEX] = 0x9000,
> + [EXT_CFG_DATA] = 0x9004,
> + [PCIE_HARD_DEBUG] = 0x4304,
> + [PCIE_INTR2_CPU_BASE] = 0x4400,
> +};
> +
> static const struct pcie_cfg_data generic_cfg = {
> .offsets = pcie_offsets,
> .type = GENERIC,
> @@ -1686,6 +1695,13 @@ static const struct pcie_cfg_data bcm7216_cfg = {
> .has_phy = true,
> };
>
> +static const struct pcie_cfg_data bcm7712_cfg = {
> + .offsets = pcie_offset_bcm7712,
> + .perst_set = brcm_pcie_perst_set_7278,
> + .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
> + .type = BCM7712,
> +};
> +
> static const struct of_device_id brcm_pcie_match[] = {
> { .compatible = "brcm,bcm2711-pcie", .data = &bcm2711_cfg },
> { .compatible = "brcm,bcm4908-pcie", .data = &bcm4908_cfg },
> @@ -1695,6 +1711,7 @@ static const struct of_device_id brcm_pcie_match[] = {
> { .compatible = "brcm,bcm7445-pcie", .data = &generic_cfg },
> { .compatible = "brcm,bcm7435-pcie", .data = &bcm7435_cfg },
> { .compatible = "brcm,bcm7425-pcie", .data = &bcm7425_cfg },
> + { .compatible = "brcm,bcm7712-pcie", .data = &bcm7712_cfg },
> {},
> };
>
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