linux-kernel - Re: [PATCH 8/9] x86/virt/tdx: Exclude memory region hole within CMR as TDMR's reserved area

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <5c3c81dc-ec15-4f7a-9807-a308082c9fc8@linux.intel.com>
Date: Fri, 5 Jul 2024 11:00:20 +0800
From: Binbin Wu <binbin.wu@...ux.intel.com>
To: "Huang, Kai" <kai.huang@...el.com>,
 "nik.borisov@...e.com" <nik.borisov@...e.com>,
 "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Cc: "Edgecombe, Rick P" <rick.p.edgecombe@...el.com>,
 "Hansen, Dave" <dave.hansen@...el.com>, "bp@...en8.de" <bp@...en8.de>,
 "x86@...nel.org" <x86@...nel.org>,
 "peterz@...radead.org" <peterz@...radead.org>, "hpa@...or.com"
 <hpa@...or.com>, "mingo@...hat.com" <mingo@...hat.com>,
 "Williams, Dan J" <dan.j.williams@...el.com>,
 "kirill.shutemov@...ux.intel.com" <kirill.shutemov@...ux.intel.com>,
 "pbonzini@...hat.com" <pbonzini@...hat.com>,
 "tglx@...utronix.de" <tglx@...utronix.de>,
 "seanjc@...gle.com" <seanjc@...gle.com>,
 "kvm@...r.kernel.org" <kvm@...r.kernel.org>,
 "Yamahata, Isaku" <isaku.yamahata@...el.com>
Subject: Re: [PATCH 8/9] x86/virt/tdx: Exclude memory region hole within CMR
 as TDMR's reserved area



On 6/19/2024 9:23 AM, Huang, Kai wrote:
[...]
>
>> furthermore the alignement checks
>> suggest it's actually some sanity checking function. Furthermore if we
>> have:"
>>
>> ORDINARY_CMR,EMPTY_CMR,ORDINARY_CMR
>>
>> (Is such a scenario even possible), in this case we'll ommit also the
>> last ordinary cmr region?
> It cannot happen.
>
> The fact is:
>
> 1) CMR base/size are 4KB aligned.  This is architectural behaviour.
> 2) TDX architecturally supports 32 CMRs maximumly;
Do you think it's worth a comment to the definition of TDX_MAX_CMRS that 
the number is architectural?

> 3) In practice, TDX can just report the 'NUM_CMRS' metadata field as 32,
> but there can be empty/null CMRs following valid CMRs.
> 4) A empty/null CMR between valid CMRs cannot happen.
>
>