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Message-ID: <fd90c6d56f95991c9a29c454e9d1ddd2a7f55340.camel@intel.com>
Date: Fri, 5 Jul 2024 09:36:25 +0000
From: "Huang, Kai" <kai.huang@...el.com>
To: "nik.borisov@...e.com" <nik.borisov@...e.com>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"binbin.wu@...ux.intel.com" <binbin.wu@...ux.intel.com>
CC: "Hansen, Dave" <dave.hansen@...el.com>, "Edgecombe, Rick P"
	<rick.p.edgecombe@...el.com>, "bp@...en8.de" <bp@...en8.de>, "x86@...nel.org"
	<x86@...nel.org>, "peterz@...radead.org" <peterz@...radead.org>,
	"hpa@...or.com" <hpa@...or.com>, "mingo@...hat.com" <mingo@...hat.com>,
	"Williams, Dan J" <dan.j.williams@...el.com>,
	"kirill.shutemov@...ux.intel.com" <kirill.shutemov@...ux.intel.com>,
	"pbonzini@...hat.com" <pbonzini@...hat.com>, "tglx@...utronix.de"
	<tglx@...utronix.de>, "seanjc@...gle.com" <seanjc@...gle.com>,
	"kvm@...r.kernel.org" <kvm@...r.kernel.org>, "Yamahata, Isaku"
	<isaku.yamahata@...el.com>
Subject: Re: [PATCH 8/9] x86/virt/tdx: Exclude memory region hole within CMR
 as TDMR's reserved area

On Fri, 2024-07-05 at 11:00 +0800, Binbin Wu wrote:
> 
> On 6/19/2024 9:23 AM, Huang, Kai wrote:
> [...]
> > 
> > > furthermore the alignement checks
> > > suggest it's actually some sanity checking function. Furthermore if we
> > > have:"
> > > 
> > > ORDINARY_CMR,EMPTY_CMR,ORDINARY_CMR
> > > 
> > > (Is such a scenario even possible), in this case we'll ommit also the
> > > last ordinary cmr region?
> > It cannot happen.
> > 
> > The fact is:
> > 
> > 1) CMR base/size are 4KB aligned.  This is architectural behaviour.
> > 2) TDX architecturally supports 32 CMRs maximumly;
> Do you think it's worth a comment to the definition of TDX_MAX_CMRS that 
> the number is architectural?
> 

OK will do. thanks.

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