lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <01c301daceb0$45221b40$cf6651c0$@samsung.com>
Date: Fri, 5 Jul 2024 16:52:22 +0900
From: "sunyeal.hong" <sunyeal.hong@...sung.com>
To: "'Jaewon Kim'" <jaewon02.kim@...sung.com>, "'Krzysztof Kozlowski'"
	<krzk@...nel.org>, "'Sylwester Nawrocki'" <s.nawrocki@...sung.com>,
	"'Chanwoo Choi'" <cw00.choi@...sung.com>, "'Alim Akhtar'"
	<alim.akhtar@...sung.com>, "'Michael	Turquette'" <mturquette@...libre.com>,
	"'Stephen Boyd'" <sboyd@...nel.org>
Cc: <linux-samsung-soc@...r.kernel.org>, <linux-clk@...r.kernel.org>,
	<linux-kernel@...r.kernel.org>
Subject: RE: [PATCH 3/5] arm64: dts: exynos: add initial CMU clock nodes in
 Exynos Auto v920

Hello Jaewon,

> -----Original Message-----
> From: Jaewon Kim <jaewon02.kim@...sung.com>
> Sent: Friday, July 5, 2024 1:42 PM
> To: Sunyeal Hong <sunyeal.hong@...sung.com>; Krzysztof Kozlowski
> <krzk@...nel.org>; Sylwester Nawrocki <s.nawrocki@...sung.com>; Chanwoo
> Choi <cw00.choi@...sung.com>; Alim Akhtar <alim.akhtar@...sung.com>;
> Michael Turquette <mturquette@...libre.com>; Stephen Boyd
> <sboyd@...nel.org>
> Cc: linux-samsung-soc@...r.kernel.org; linux-clk@...r.kernel.org; linux-
> kernel@...r.kernel.org
> Subject: Re: [PATCH 3/5] arm64: dts: exynos: add initial CMU clock nodes
> in Exynos Auto v920
> 
> Hi Sunyeal,
> 
> 
> On 7/5/24 11:11, Sunyeal Hong wrote:
> > Add cmu_top, cmu_peric0 clock nodes and switch USI clocks instead of
> > dummy fixed-rate-clock.
> >
> > Signed-off-by: Sunyeal Hong <sunyeal.hong@...sung.com>
> > ---
> >   .../arm64/boot/dts/exynos/exynosautov920.dtsi | 40 +++++++++++++------
> >   1 file changed, 27 insertions(+), 13 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
> > b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
> > index c1c8566d74f5..1659c0a375c9 100644
> > --- a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
> > +++ b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
> > @@ -6,6 +6,7 @@
> >    *
> >    */
> >
> > +#include <dt-bindings/clock/samsung,exynosautov920.h>
> >   #include <dt-bindings/interrupt-controller/arm-gic.h>
> >   #include <dt-bindings/soc/samsung,exynos-usi.h>
> >
> > @@ -38,17 +39,6 @@ xtcxo: clock {
> >   		clock-output-names = "oscclk";
> >   	};
> >
> > -	/*
> > -	 * FIXME: Keep the stub clock for serial driver, until proper clock
> > -	 * driver is implemented.
> > -	 */
> > -	clock_usi: clock-usi {
> > -		compatible = "fixed-clock";
> > -		#clock-cells = <0>;
> > -		clock-frequency = <200000000>;
> > -		clock-output-names = "usi";
> > -	};
> > -
> >   	cpus: cpus {
> >   		#address-cells = <2>;
> >   		#size-cells = <0>;
> > @@ -182,6 +172,28 @@ chipid@...00000 {
> >   			reg = <0x10000000 0x24>;
> >   		};
> >
> > +		cmu_peric0: clock-controller@...00000 {
> > +			compatible = "samsung,exynosautov920-cmu-peric0";
> > +			reg = <0x10800000 0x8000>;
> > +			#clock-cells = <1>;
> > +
> > +			clocks = <&xtcxo>,
> > +				 <&cmu_top DOUT_CLKCMU_PERIC0_NOC>,
> > +				 <&cmu_top DOUT_CLKCMU_PERIC0_IP>;
> > +			clock-names = "oscclk",
> > +				      "dout_clkcmu_peric0_noc",
> > +				      "dout_clkcmu_peric0_ip";
> > +		};
> > +
> > +		cmu_top: clock-controller@...00000 {
> > +			compatible = "samsung,exynosautov920-cmu-top";
> > +			reg = <0x11000000 0x8000>;
> > +			#clock-cells = <1>;
> > +
> > +			clocks = <&xtcxo>;
> > +			clock-names = "oscclk";
> > +		};
> > +
> >   		gic: interrupt-controller@...00000 {
> >   			compatible = "arm,gic-v3";
> >   			#interrupt-cells = <3>;
> > @@ -213,7 +225,8 @@ usi_0: usi@...800c0 {
> >   			#address-cells = <1>;
> >   			#size-cells = <1>;
> >   			ranges;
> > -			clocks = <&clock_usi>, <&clock_usi>;
> > +			clocks = <&cmu_peric0 CLK_DOUT_PERIC0_USI00_USI>,
> > +				 <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>;
> 
> it seems that the clocks have been switched.
> CLK_DOUT_PERIC0_USI00_USI is ipclk and CLK_MOUT_PERIC0_NOC_USER is pclk of
> USI.
> 
> 
> 
> >   			clock-names = "pclk", "ipclk";
> >   			status = "disabled";
> >
> > @@ -224,7 +237,8 @@ serial_0: serial@...80000 {
> >   				interrupts = <GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH>;
> >   				pinctrl-names = "default";
> >   				pinctrl-0 = <&uart0_bus>;
> > -				clocks = <&clock_usi>, <&clock_usi>;
> > +				clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>,
> > +					 <&cmu_peric0 CLK_DOUT_PERIC0_USI00_USI>;
> >   				clock-names = "uart", "clk_uart_baud0";
> >   				samsung,uart-fifosize = <256>;
> >   				status = "disabled";
> 
> Thanks
> Jaewon Kim
> 

I will change ipclk and pclk clock node as you requested.

Thanks,
Sunyeal Hong


Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ