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Message-ID: <20240708165056.000012d9@Huawei.com>
Date: Mon, 8 Jul 2024 16:50:56 +0100
From: Jonathan Cameron <Jonathan.Cameron@...wei.com>
To: Mauro Carvalho Chehab <mchehab+huawei@...nel.org>
CC: Borislav Petkov <bp@...en8.de>, Tony Luck <tony.luck@...el.com>, "Ard
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Subject: Re: [PATCH 5/6] efi/cper: align ARM CPER type with UEFI 2.9A/2.10
specs
On Mon, 8 Jul 2024 13:18:14 +0200
Mauro Carvalho Chehab <mchehab+huawei@...nel.org> wrote:
> Up to UEFI spec, the type byte of CPER struct for ARM processor was
Up to UEFI spec XXX?
> defined simply as:
>
> Type at byte offset 4:
>
> - Cache error
> - TLB Error
> - Bus Error
> - Micro-architectural Error
> All other values are reserved
>
> Yet, there was no information about how this would be encoded.
>
> Spec 2.9A errata corrected it by defining:
>
> - Bit 1 - Cache Error
> - Bit 2 - TLB Error
> - Bit 3 - Bus Error
> - Bit 4 - Micro-architectural Error
> All other values are reserved
>
> That actually aligns with the values already defined on older
> versions at N.2.4.1. Generic Processor Error Section.
>
> Spec 2.10 also preserve the same encoding as 2.9A
>
> Adjust CPER and GHES handling code for both generic and ARM
> processors to properly handle UEFI 2.9A and 2.10 encoding.
>
> Link: https://uefi.org/specs/UEFI/2.10/Apx_N_Common_Platform_Error_Record.html#arm-processor-error-information
> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@...nel.org>
With above tidied up.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@...wei.com>
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