linux-kernel - Re: [PATCH v1] arm64: dts: rockchip: Add missing pinctrl for PCIe30x4 node

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Message-ID: <CANAwSgTRW1zQcZBb+8Yzu2hgqPxVopG+8c4Ng+QNrcGjBXOC8g@mail.gmail.com>
Date: Wed, 10 Jul 2024 22:00:37 +0530
From: Anand Moon <linux.amoon@...il.com>
To: Heiko Stübner <heiko@...ech.de>
Cc: Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, 
	Conor Dooley <conor+dt@...nel.org>, devicetree@...r.kernel.org, 
	linux-arm-kernel@...ts.infradead.org, linux-rockchip@...ts.infradead.org, 
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH v1] arm64: dts: rockchip: Add missing pinctrl for PCIe30x4 node

Hi Heiko,

Thanks for your review comments.

On Wed, 10 Jul 2024 at 20:24, Heiko Stübner <heiko@...ech.de> wrote:
>
> Hi,
>
> Am Mittwoch, 10. Juli 2024, 16:19:56 CEST schrieb Anand Moon:
> > Add missing pinctrl settings for PCIe 3.0 x4 clock request and wake
> > signals. Rename node from 'pcie3' to 'pcie30x4' to align with schematic
> > nomenclature.
> >
> > Signed-off-by: Anand Moon <linux.amoon@...il.com>
> > ---
> >  .../boot/dts/rockchip/rk3588-rock-5b.dts      | 20 +++++++++++++------
> >  1 file changed, 14 insertions(+), 6 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
> > index 2e7512676b7e..a9b55b7996cf 100644
> > --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
> > +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
> > @@ -301,7 +301,7 @@ &pcie30phy {
> >
> >  &pcie3x4 {
> >       pinctrl-names = "default";
> > -     pinctrl-0 = <&pcie3_rst>;
> > +     pinctrl-0 = <&pcie30x4_perstn_m1 &pcie30x4_clkreqn_m1 &pcie30x4_waken_m1>;
> >       reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
> >       vpcie3v3-supply = <&vcc3v3_pcie30>;
> >       status = "okay";
> > @@ -340,14 +340,22 @@ pcie2_2_rst: pcie2-2-rst {
> >               };
> >       };
> >
> > -     pcie3 {
> > -             pcie3_rst: pcie3-rst {
> > -                     rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
> > -             };
> > -
> > +     pcie30x4 {
> >               pcie3_vcc3v3_en: pcie3-vcc3v3-en {
> >                       rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
> >               };
> > +
> > +             pcie30x4_clkreqn_m1: pcie30x4-clkreqn-m1 {
> > +                     rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>;
> > +             };
> > +
> > +             pcie30x4_waken_m1: pcie30x4-waken-m1 {
> > +                     rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>;
> > +             };
> > +
> > +             pcie30x4_perstn_m1: pcie30x4-perstn-m1 {
> > +                     rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
> > +             };
>
> I'm not sure what you're going for here, but defining them as gpio makes
> them essentially unused? Shouldn't they go to the pcie controller?
>

Ok, Each component of PCIe communication to have the following
control signals #PERST # WAKE and CLKREQ from root complex to endpoint.

> From what I found for example
> The PERST# signal is used to indicate when the power supply is within its specified voltage tolerance and is stable.
>

PERST is referred to as a fundamental reset. PERST should be held low
until all the power rails
in the system and the reference clock are stable. A transition from
low to high in this signal usually
indicates the beginning of link initialization.

> At least you'll need to explain more in the commit message.
>
Ok,
WAKE and CLKREQ signals are used to transition to and from low-power states.
WAKE signal is an active-low signal that is used to return the PCIe
interface to an active state
when in a low-power state.
CLKREQ signal is also an active-low signal and is used to request the
reference clock.
>
I will work on and update in the next version.
>
> Heiko

Thanks
-Anand