linux-kernel - RE: [PATCH v2 3/4] clk: samsung: clk-pll: Add support for pll

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Message-ID: <000201dad26f$b18c3690$14a4a3b0$@samsung.com>
Date: Wed, 10 Jul 2024 11:20:12 +0900
From: "sunyeal.hong" <sunyeal.hong@...sung.com>
To: "'Alim Akhtar'" <alim.akhtar@...sung.com>, "'Krzysztof Kozlowski'"
	<krzk@...nel.org>, "'Sylwester Nawrocki'" <s.nawrocki@...sung.com>,
	"'Chanwoo Choi'" <cw00.choi@...sung.com>, "'Michael Turquette'"
	<mturquette@...libre.com>, "'Stephen Boyd'" <sboyd@...nel.org>, "'Rob
 Herring'" <robh@...nel.org>, "'Conor Dooley'" <conor+dt@...nel.org>
Cc: <linux-samsung-soc@...r.kernel.org>, <linux-clk@...r.kernel.org>,
	<devicetree@...r.kernel.org>, <linux-arm-kernel@...ts.infradead.org>,
	<linux-kernel@...r.kernel.org>
Subject: RE: [PATCH v2 3/4] clk: samsung: clk-pll: Add support for pll_531x

Hello Alim,

> -----Original Message-----
> From: Alim Akhtar <alim.akhtar@...sung.com>
> Sent: Monday, July 8, 2024 8:58 PM
> To: 'Sunyeal Hong' <sunyeal.hong@...sung.com>; 'Krzysztof Kozlowski'
> <krzk@...nel.org>; 'Sylwester Nawrocki' <s.nawrocki@...sung.com>; 'Chanwoo
> Choi' <cw00.choi@...sung.com>; 'Michael Turquette'
> <mturquette@...libre.com>; 'Stephen Boyd' <sboyd@...nel.org>; 'Rob
> Herring' <robh@...nel.org>; 'Conor Dooley' <conor+dt@...nel.org>
> Cc: linux-samsung-soc@...r.kernel.org; linux-clk@...r.kernel.org;
> devicetree@...r.kernel.org; linux-arm-kernel@...ts.infradead.org; linux-
> kernel@...r.kernel.org
> Subject: RE: [PATCH v2 3/4] clk: samsung: clk-pll: Add support for
> pll_531x
> 
> Hello Sunyeal,
> 
> > -----Original Message-----
> > From: Sunyeal Hong <sunyeal.hong@...sung.com>
> > Sent: Monday, July 8, 2024 4:44 AM
> > To: Krzysztof Kozlowski <krzk@...nel.org>; Sylwester Nawrocki
> > <s.nawrocki@...sung.com>; Chanwoo Choi <cw00.choi@...sung.com>; Alim
> > Akhtar <alim.akhtar@...sung.com>; Michael Turquette
> > <mturquette@...libre.com>; Stephen Boyd <sboyd@...nel.org>; Rob
> > Herring <robh@...nel.org>; Conor Dooley <conor+dt@...nel.org>
> > Cc: linux-samsung-soc@...r.kernel.org; linux-clk@...r.kernel.org;
> > devicetree@...r.kernel.org; linux-arm-kernel@...ts.infradead.org;
> > linux- kernel@...r.kernel.org; Sunyeal Hong <sunyeal.hong@...sung.com>
> > Subject: [PATCH v2 3/4] clk: samsung: clk-pll: Add support for
> > pll_531x
> >
> > pll531x PLL is used in Exynos Auto v920 SoC for shared pll.
> > pll531x: Integer/fractional PLL with mid frequency FVCO (800 to 3120
> > MHz)
> >
> > PLL531x
> > FOUT = (MDIV + F/2^32-F[31]) * FIN/(PDIV x 2^SDIV)
> >
> Any reason for not mentioning equation for integer PLL?
> 
If the F value is 0, it operates as an integer PLL. 
> > Signed-off-by: Sunyeal Hong <sunyeal.hong@...sung.com>
> > ---
> Anyway, LGTM,
> 
> Reviewed-by: Alim Akhtar <alim.akhtar@...sung.com>
> 
> >  drivers/clk/samsung/clk-pll.c | 45
> > +++++++++++++++++++++++++++++++++++
> >  drivers/clk/samsung/clk-pll.h |  1 +
> >  2 files changed, 46 insertions(+)
> >
> > diff --git a/drivers/clk/samsung/clk-pll.c
> > b/drivers/clk/samsung/clk-pll.c index
> > 4be879ab917e..b3bcef074ab7 100644
> > --- a/drivers/clk/samsung/clk-pll.c
> > +++ b/drivers/clk/samsung/clk-pll.c
> > @@ -1261,6 +1261,48 @@ static const struct clk_ops
> > samsung_pll2650xx_clk_min_ops = {
> >  	.recalc_rate = samsung_pll2650xx_recalc_rate,  };
> >
> > +/*
> > + * PLL531X Clock Type
> > + */
> > +/* Maximum lock time can be 500 * PDIV cycles */
> > +#define PLL531X_LOCK_FACTOR		(500)
> > +#define PLL531X_MDIV_MASK		(0x3FF)
> > +#define PLL531X_PDIV_MASK		(0x3F)
> > +#define PLL531X_SDIV_MASK		(0x7)
> > +#define PLL531X_FDIV_MASK		(0xFFFF)
> > +#define PLL531X_MDIV_SHIFT		(16)
> > +#define PLL531X_PDIV_SHIFT		(8)
> > +#define PLL531X_SDIV_SHIFT		(0)
> > +
> > +static unsigned long samsung_pll531x_recalc_rate(struct clk_hw *hw,
> > +						 unsigned long parent_rate)
> > +{
> > +	struct samsung_clk_pll *pll = to_clk_pll(hw);
> > +	u32 mdiv, pdiv, sdiv, pll_con0, pll_con8;
> > +	s32 fdiv;
> > +	u64 fout = parent_rate;
> > +
> > +	pll_con0 = readl_relaxed(pll->con_reg);
> > +	pll_con8 = readl_relaxed(pll->con_reg + 20);
> > +	mdiv = (pll_con0 >> PLL531X_MDIV_SHIFT) & PLL531X_MDIV_MASK;
> > +	pdiv = (pll_con0 >> PLL531X_PDIV_SHIFT) & PLL531X_PDIV_MASK;
> > +	sdiv = (pll_con0 >> PLL531X_SDIV_SHIFT) & PLL531X_SDIV_MASK;
> > +	fdiv = (s32)(pll_con8 & PLL531X_FDIV_MASK);
> > +
> > +	if (fdiv >> 31)
> > +		mdiv--;
> > +
> > +	fout *= ((u64)mdiv << 24) + (fdiv >> 8);
> > +	do_div(fout, (pdiv << sdiv));
> > +	fout >>= 24;
> > +
> > +	return (unsigned long)fout;
> > +}
> > +
> > +static const struct clk_ops samsung_pll531x_clk_ops = {
> > +	.recalc_rate = samsung_pll531x_recalc_rate, };
> > +
> >  static void __init _samsung_clk_register_pll(struct
> > samsung_clk_provider *ctx,
> >  				const struct samsung_pll_clock *pll_clk)  { @@ -
> 1394,6 +1436,9 @@
> > static void __init _samsung_clk_register_pll(struct
> > samsung_clk_provider *ctx,
> >  		else
> >  			init.ops = &samsung_pll2650xx_clk_ops;
> >  		break;
> > +	case pll_531x:
> > +		init.ops = &samsung_pll531x_clk_ops;
> > +		break;
> >  	default:
> >  		pr_warn("%s: Unknown pll type for pll clk %s\n",
> >  			__func__, pll_clk->name);
> > diff --git a/drivers/clk/samsung/clk-pll.h
> > b/drivers/clk/samsung/clk-pll.h index ffd3d52c0dec..ce9d6f21f993
> > 100644
> > --- a/drivers/clk/samsung/clk-pll.h
> > +++ b/drivers/clk/samsung/clk-pll.h
> > @@ -41,6 +41,7 @@ enum samsung_pll_type {
> >  	pll_0516x,
> >  	pll_0517x,
> >  	pll_0518x,
> > +	pll_531x,
> >  };
> >
> >  #define PLL_RATE(_fin, _m, _p, _s, _k, _ks) \
> > --
> > 2.45.2
>