linux-kernel - Re: [PATCH v3 2/3] clk: qcom: dispcc-sm8650: add missing CLK_SET_RATE

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Message-ID: <9ad10d92-d755-4fae-b206-6e8648be6d48@linaro.org>
Date: Tue, 16 Jul 2024 14:32:22 +0200
From: Neil Armstrong <neil.armstrong@...aro.org>
To: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
Cc: Bjorn Andersson <andersson@...nel.org>,
 Michael Turquette <mturquette@...libre.com>, Stephen Boyd
 <sboyd@...nel.org>, Konrad Dybcio <konrad.dybcio@...aro.org>,
 Taniya Das <quic_tdas@...cinc.com>, linux-arm-msm@...r.kernel.org,
 linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v3 2/3] clk: qcom: dispcc-sm8650: add missing
 CLK_SET_RATE_PARENT flag

On 16/07/2024 13:20, Dmitry Baryshkov wrote:
> On Tue, Jul 16, 2024 at 11:05:22AM GMT, Neil Armstrong wrote:
>> Add the missing CLK_SET_RATE_PARENT for the byte0_div_clk_src
>> and byte1_div_clk_src, the clock rate should propagate to
>> the corresponding _clk_src.
>>
>> Fixes: 9e939f008338 ("clk: qcom: add the SM8650 Display Clock Controller driver")
>> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
>> Signed-off-by: Neil Armstrong <neil.armstrong@...aro.org>
>> ---
>>   drivers/clk/qcom/dispcc-sm8650.c | 2 ++
>>   1 file changed, 2 insertions(+)
> 
> This doesn't seem correct, the byte1_div_clk_src is a divisor, so the
> rate should not be propagated. Other platforms don't set this flag.
> 

Why not ? the disp_cc_mdss_byte1_clk_src has CLK_SET_RATE_PARENT and a div_table,
and we only pass DISP_CC_MDSS_BYTE1_CLK to the dsi controller.

Neil