linux-kernel - RE: [PATCH v2 0/8] PCI: Align small (<4k) BARs

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Message-ID: <0da056616de54589bc1d4b95dcdf5d3d@AcuMS.aculab.com>
Date: Wed, 17 Jul 2024 13:15:29 +0000
From: David Laight <David.Laight@...LAB.COM>
To: 'Stewart Hildebrand' <stewart.hildebrand@....com>, Bjorn Helgaas
	<bhelgaas@...gle.com>, Thomas Gleixner <tglx@...utronix.de>, Ingo Molnar
	<mingo@...hat.com>, Borislav Petkov <bp@...en8.de>, Dave Hansen
	<dave.hansen@...ux.intel.com>, "H. Peter Anvin" <hpa@...or.com>, "Michael
 Ellerman" <mpe@...erman.id.au>, Nicholas Piggin <npiggin@...il.com>,
	Christophe Leroy <christophe.leroy@...roup.eu>, "Naveen N. Rao"
	<naveen.n.rao@...ux.ibm.com>, Thomas Zimmermann <tzimmermann@...e.de>, "Arnd
 Bergmann" <arnd@...db.de>, Sam Ravnborg <sam@...nborg.org>, Yongji Xie
	<elohimes@...il.com>, Ilpo Järvinen
	<ilpo.jarvinen@...ux.intel.com>
CC: "x86@...nel.org" <x86@...nel.org>, "linux-pci@...r.kernel.org"
	<linux-pci@...r.kernel.org>, "linux-kernel@...r.kernel.org"
	<linux-kernel@...r.kernel.org>, "linuxppc-dev@...ts.ozlabs.org"
	<linuxppc-dev@...ts.ozlabs.org>
Subject: RE: [PATCH v2 0/8] PCI: Align small (<4k) BARs

From: Stewart Hildebrand
> Sent: 16 July 2024 20:33
> 
> This series sets the default minimum resource alignment to 4k for memory
> BARs. In preparation, it makes an optimization and addresses some corner
> cases observed when reallocating BARs. I consider the prepapatory
> patches to be prerequisites to changing the default BAR alignment.

Should the BARs be page aligned on systems with large pages?
At least as an option for hypervisor pass-through and any than can be mmap()ed
into userspace.

Does any hardware actually have 'silly numbers' of small memory BARs?

I have a vague memory of some ethernet controllers having lots of (?)
virtual devices that might have separate registers than can be mapped
out to a hypervisor.
Expanding those to a large page might be problematic - but needed for security.

For more normal hardware just ensuring that two separate targets don't share
a page while allowing (eg) two 1k BAR to reside in the same 64k page would
give some security.

Aligning a small MSIX BAR is unlikely to have any effect on the address
space utilisation (for PCIe) since the bridge will assign a power of two
sized block - with a big pad (useful for generating pcie errors!)

	David

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