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Message-ID: <Zp4HCPYId4sjd32Q@linaro.org>
Date: Mon, 22 Jul 2024 09:15:20 +0200
From: Stephan Gerhold <stephan.gerhold@...aro.org>
To: Rob Clark <robdclark@...il.com>
Cc: linux-arm-msm@...r.kernel.org, Doug Anderson <dianders@...omium.org>,
Dmitry Baryshkov <dmitry.baryshkov@...aro.org>,
Abel Vesa <abel.vesa@...aro.org>,
Rob Clark <robdclark@...omium.org>,
Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konrad.dybcio@...aro.org>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" <devicetree@...r.kernel.org>,
open list <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v2 2/2] arm64: dts: qcom: x1e80100-yoga: Update panel
bindings
On Fri, Jul 19, 2024 at 11:52:50AM -0700, Rob Clark wrote:
> From: Rob Clark <robdclark@...omium.org>
>
> Use the correct panel compatible, and wire up enable-gpio. It is wired
> up in the same way as the x1e80100-crd.
>
> Signed-off-by: Rob Clark <robdclark@...omium.org>
> ---
> .../boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts | 13 ++++++++++++-
> 1 file changed, 12 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts b/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts
> index f569f0fbd1fc..28a6ea5a24fd 100644
> --- a/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts
> +++ b/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts
> @@ -592,9 +592,13 @@ &mdss_dp3 {
>
> aux-bus {
> panel {
> - compatible = "edp-panel";
> + compatible = "samsung,atna45dc02", "samsung,atna33xc20";
> + enable-gpios = <&pmc8380_3_gpios 4 GPIO_ACTIVE_HIGH>;
> power-supply = <&vreg_edp_3p3>;
>
> + pinctrl-0 = <&edp_bl_en>;
> + pinctrl-names = "default";
> +
> port {
> edp_panel_in: endpoint {
> remote-endpoint = <&mdss_dp3_out>;
> @@ -663,6 +667,13 @@ &pcie6a_phy {
> status = "okay";
> };
>
> +&pmc8380_3_gpios {
> + edp_bl_en: edp-bl-en-state {
> + pins = "gpio4";
> + function = "normal";
> + };
Did you omit the "power-source" here on purpose? It works without
because the firmware already configures this pin, but ideally we should
provide the full configuration.
In /sys/kernel/debug/gpio you can check how the firmware has configured
the pin. It is probably exactly the same as for the CRD.
Thanks,
Stephan
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