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Message-ID: <CAA8EJpovn=eAj21R=Q7mDXcb1SmHpRhYNnNpHpx+YHyaT7S0tw@mail.gmail.com>
Date: Fri, 26 Jul 2024 13:43:55 +0300
From: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
To: "Satya Priya Kakitapalli (Temp)" <quic_skakitap@...cinc.com>
Cc: Bjorn Andersson <andersson@...nel.org>, Konrad Dybcio <konrad.dybcio@...aro.org>, 
	Michael Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>, 
	Abhishek Sahu <absahu@...eaurora.org>, Rob Herring <robh@...nel.org>, 
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>, Conor Dooley <conor+dt@...nel.org>, 
	Stephen Boyd <sboyd@...eaurora.org>, linux-arm-msm@...r.kernel.org, 
	linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org, 
	devicetree@...r.kernel.org, Ajit Pandey <quic_ajipan@...cinc.com>, 
	Imran Shaik <quic_imrashai@...cinc.com>, Taniya Das <quic_tdas@...cinc.com>, 
	Jagadeesh Kona <quic_jkona@...cinc.com>, "Bryan O'Donoghue" <bryan.odonoghue@...aro.org>
Subject: Re: [PATCH v2 5/6] clk: qcom: Add camera clock controller driver for SM8150

On Fri, 26 Jul 2024 at 11:26, Satya Priya Kakitapalli (Temp)
<quic_skakitap@...cinc.com> wrote:
>
>
> >>>>> - I see that most if not all RCG clocks use rcg2_shared ops instead of
> >>>>>      using simple rcg2 ops, could you please clarify that?
> >>>> As per the HW design recommendation, RCG needs to be parked at a safe
> >>>> clock source(XO) in the disable path, shared_ops is used to achieve the
> >>>> same.
> >>> Does it apply to SM8150? For example, on SM8250 RCG2s are not parked.
> >>
> >> Yes, it applies to SM8150.
> > Should the same logic be applied to other chipsets supported upstream?
> > If this is the case, which chipsets?
>
>
> I will evaluate for what all chipsets it is applicable and post a series
> to fix it.

Thanks a lot!


-- 
With best wishes
Dmitry

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