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Message-Id: <D2ZHJ765LUGP.2KTA46P1BL75X@walle.cc>
Date: Fri, 26 Jul 2024 14:55:28 +0200
From: "Michael Walle" <michael@...le.cc>
To: "Mahapatra, Amit Kumar" <amit.kumar-mahapatra@....com>, "Tudor Ambarus"
<tudor.ambarus@...aro.org>, "broonie@...nel.org" <broonie@...nel.org>,
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Subject: Re: [PATCH v11 07/10] mtd: spi-nor: Add stacked memories support in
spi-nor
Hi,
> Based on the inputs/suggestions from Tudor, i am planning to add a new
> layer between the SPI-NOR and MTD layers to support stacked and parallel
> configurations. This new layer will be part of the spi-nor and located in
> mtd/spi-nor/
Will AMD submit to maintain this layer? What happens if the
maintainer will leave AMD? TBH, personally, I don't like to
maintain such a niche feature.
I'd really like to see some use cases and performance reports for
this, like actual boards (and no evaluation boards don't count). Why
wouldn't someone just use an octal flash?
And as already mentioned there is also mtdcat, which seems to
duplicate some features?
-michael
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