linux-kernel - Re: [PATCH v11 07/10] mtd: spi-nor: Add stacked memories support in spi-nor

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Message-ID: <e1587f61-f765-4a22-b06e-71387cc49c4d@amd.com>
Date: Wed, 31 Jul 2024 10:58:26 +0200
From: Michal Simek <michal.simek@....com>
To: Michael Walle <michael@...le.cc>,
 "Mahapatra, Amit Kumar" <amit.kumar-mahapatra@....com>,
 Tudor Ambarus <tudor.ambarus@...aro.org>,
 "broonie@...nel.org" <broonie@...nel.org>,
 "pratyush@...nel.org" <pratyush@...nel.org>,
 "miquel.raynal@...tlin.com" <miquel.raynal@...tlin.com>,
 "richard@....at" <richard@....at>, "vigneshr@...com" <vigneshr@...com>,
 "sbinding@...nsource.cirrus.com" <sbinding@...nsource.cirrus.com>,
 "lee@...nel.org" <lee@...nel.org>,
 "james.schulman@...rus.com" <james.schulman@...rus.com>,
 "david.rhodes@...rus.com" <david.rhodes@...rus.com>,
 "rf@...nsource.cirrus.com" <rf@...nsource.cirrus.com>,
 "perex@...ex.cz" <perex@...ex.cz>, "tiwai@...e.com" <tiwai@...e.com>
Cc: "linux-spi@...r.kernel.org" <linux-spi@...r.kernel.org>,
 "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
 "linux-mtd@...ts.infradead.org" <linux-mtd@...ts.infradead.org>,
 "nicolas.ferre@...rochip.com" <nicolas.ferre@...rochip.com>,
 "alexandre.belloni@...tlin.com" <alexandre.belloni@...tlin.com>,
 "claudiu.beznea@...on.dev" <claudiu.beznea@...on.dev>,
 "linux-arm-kernel@...ts.infradead.org"
 <linux-arm-kernel@...ts.infradead.org>,
 "alsa-devel@...a-project.org" <alsa-devel@...a-project.org>,
 "patches@...nsource.cirrus.com" <patches@...nsource.cirrus.com>,
 "linux-sound@...r.kernel.org" <linux-sound@...r.kernel.org>,
 "git (AMD-Xilinx)" <git@....com>,
 "amitrkcian2002@...il.com" <amitrkcian2002@...il.com>,
 Conor Dooley <conor.dooley@...rochip.com>,
 "beanhuo@...ron.com" <beanhuo@...ron.com>
Subject: Re: [PATCH v11 07/10] mtd: spi-nor: Add stacked memories support in
 spi-nor

Hi Michael,

On 7/26/24 14:55, Michael Walle wrote:
> Hi,
> 
>> Based on the inputs/suggestions from Tudor, i am planning to add a new
>> layer between the SPI-NOR and MTD layers to support stacked and parallel
>> configurations. This new layer will be part of the spi-nor and located in
>> mtd/spi-nor/
> 
> Will AMD submit to maintain this layer? What happens if the
> maintainer will leave AMD? TBH, personally, I don't like to
> maintain such a niche feature.
> I'd really like to see some use cases and performance reports for
> this, like actual boards (and no evaluation boards don't count). Why
> wouldn't someone just use an octal flash?

AMD/Xilinx is not creating products that's why we don't have data on actual 
boards but I don't really understand why evaluation boards don't count. A lot of 
customers are taking schematics from us and removing parts which they don't need 
and add their custom part.

But one product for parallel configuration which is publicly saying that it is 
using it is for example this SOM.
https://shop.trenz-electronic.de/en/TE0820-05-2AI21MA-MPSoC-Module-with-AMD-Zynq-UltraScale-ZU2CG-1I-2-GByte-DDR4-SDRAM-4-x-5-cm

I am not marketing guy to tell if there is any other which publicly saying we 
are using this feature but we can only develop/support/maintain support for 
these configurations on our evaluation boards because that's what we have access 
to and what we know how it is done.

Also performance numbers from us can be only provided against our evaluation boards.

Thanks,
Michal