linux-kernel - [PATCH v2 0/4] arm64: dts: renesas: Correct GICD and GICR sizes

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Message-Id: <20240730122436.350013-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
Date: Tue, 30 Jul 2024 13:24:32 +0100
From: Prabhakar <prabhakar.csengg@...il.com>
To: Geert Uytterhoeven <geert+renesas@...der.be>,
	Marc Zyngier <maz@...nel.org>,
	Magnus Damm <magnus.damm@...il.com>,
	Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>
Cc: linux-renesas-soc@...r.kernel.org,
	devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org,
	Prabhakar <prabhakar.csengg@...il.com>,
	Biju Das <biju.das.jz@...renesas.com>,
	Fabrizio Castro <fabrizio.castro.jz@...esas.com>,
	Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: [PATCH v2 0/4] arm64: dts: renesas: Correct GICD and GICR sizes

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>

Hi All,

This patch series aims to correct GICD and GICR sizes on RZ/G2L(LC),
RZ/G2UL, RZ/V2L and RZ/G3S SoCs. These SoCs are equipped with GIC-600.

GIC-600 supports MBI by default, so GICD size is set to 128kB.
On RZ/G2UL and RZ/G3S SoC despite being single core the GICR size is set
to 256kB as dumping the GICR_IIDR register shows it has two instances of
GICR.

v1->v2
- Dropped changes for single core
- Updated commit message

Cheers,
Prabhakar

Lad Prabhakar (4):
  arm64: dts: renesas: r9a08g045: Correct GICD and GICR sizes
  arm64: dts: renesas: r9a07g043u: Correct GICD and GICR sizes
  arm64: dts: renesas: r9a07g054: Correct GICD and GICR sizes
  arm64: dts: renesas: r9a07g044: Correct GICD and GICR sizes

 arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | 4 ++--
 arch/arm64/boot/dts/renesas/r9a07g044.dtsi  | 4 ++--
 arch/arm64/boot/dts/renesas/r9a07g054.dtsi  | 4 ++--
 arch/arm64/boot/dts/renesas/r9a08g045.dtsi  | 4 ++--
 4 files changed, 8 insertions(+), 8 deletions(-)

-- 
2.34.1