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Message-ID: <20240801161005.120111-1-alessandro.zanni87@gmail.com>
Date: Thu, 1 Aug 2024 18:10:02 +0200
From: Alessandro Zanni <alessandro.zanni87@...il.com>
To: robh@...nel.org,
krzk+dt@...nel.org,
conor+dt@...nel.org,
skhan@...uxfoundation.org
Cc: Alessandro Zanni <alessandro.zanni87@...il.com>,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: [PATCH v3] dt-bindings: edac: Add Altera SOCFPGA SDRAM EDAC binding
Convert the device tree bindings for the Altera PCIe MSI controller
Signed-off-by: Alessandro Zanni <alessandro.zanni87@...il.com>
---
Notes:
v3: moved yaml file from arm/altera to the edac folder, removed items keys, added general node names
.../arm/altera/socfpga-sdram-edac.txt | 15 -------
.../bindings/edac/altr,sdram-edac.yaml | 44 +++++++++++++++++++
2 files changed, 44 insertions(+), 15 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt
create mode 100644 Documentation/devicetree/bindings/edac/altr,sdram-edac.yaml
diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt
deleted file mode 100644
index f5ad0ff69fae..000000000000
--- a/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt
+++ /dev/null
@@ -1,15 +0,0 @@
-Altera SOCFPGA SDRAM Error Detection & Correction [EDAC]
-The EDAC accesses a range of registers in the SDRAM controller.
-
-Required properties:
-- compatible : should contain "altr,sdram-edac" or "altr,sdram-edac-a10"
-- altr,sdr-syscon : phandle of the sdr module
-- interrupts : Should contain the SDRAM ECC IRQ in the
- appropriate format for the IRQ controller.
-
-Example:
- sdramedac {
- compatible = "altr,sdram-edac";
- altr,sdr-syscon = <&sdr>;
- interrupts = <0 39 4>;
- };
diff --git a/Documentation/devicetree/bindings/edac/altr,sdram-edac.yaml b/Documentation/devicetree/bindings/edac/altr,sdram-edac.yaml
new file mode 100644
index 000000000000..31bcee4274fa
--- /dev/null
+++ b/Documentation/devicetree/bindings/edac/altr,sdram-edac.yaml
@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/edac/altr,sdram-edac.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Altera SOCFPGA SDRAM Error Detection & Correction [EDAC]
+
+maintainers:
+ - Dinh Nguyen <dinguyen@...nel.org>
+
+description:
+ The EDAC accesses a range of registers in the SDRAM controller.
+
+properties:
+ compatible:
+ enum:
+ - altr,sdram-edac
+ - altr,sdram-edac-a10
+
+ altr,sdr-syscon:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle of the sdr module
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - altr,sdr-syscon
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ memory-controller {
+ compatible = "altr,sdram-edac";
+ altr,sdr-syscon = <&sdr>;
+ interrupts = <0 39 4>;
+ };
+
+...
--
2.43.0
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