linux-kernel - Re: [PATCH V7] LoongArch: Add AVEC irqchip support

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <cff37371-0692-0db5-cb14-74c519eb1c56@loongson.cn>
Date: Sat, 3 Aug 2024 14:40:24 +0800
From: Tianyang Zhang <zhangtianyang@...ngson.cn>
To: Thomas Gleixner <tglx@...utronix.de>, Huacai Chen <chenhuacai@...nel.org>
Cc: corbet@....net, alexs@...nel.org, siyanteng@...ngson.cn,
 kernel@...0n.name, jiaxun.yang@...goat.com, gaoliang@...ngson.cn,
 wangliupu@...ngson.cn, lvjianmin@...ngson.cn, yijun@...ngson.cn,
 mhocko@...e.com, akpm@...ux-foundation.org, dianders@...omium.org,
 maobibo@...ngson.cn, xry111@...111.site, zhaotianrui@...ngson.cn,
 nathan@...nel.org, yangtiezhu@...ngson.cn, zhoubinbin@...ngson.cn,
 loongarch@...ts.linux.dev, linux-doc@...r.kernel.org,
 linux-kernel@...r.kernel.org, Huacai Chen <chenhuacai@...ngson.cn>
Subject: Re: [PATCH V7] LoongArch: Add AVEC irqchip support

Hi, Thomas

在 2024/7/30 下午7:29, Thomas Gleixner 写道:
> Huacai!
>
> On Tue, Jul 30 2024 at 16:51, Huacai Chen wrote:
>> On Fri, Jul 26, 2024 at 11:12 PM Thomas Gleixner <tglx@...utronix.de> wrote:
>>>> +     while (true) {
>>>> +             vector = csr_read64(LOONGARCH_CSR_IRR);
>>>> +             if (vector & IRR_INVALID_MASK)
>>>> +                     break;
>>>> +
>>>> +             vector &= IRR_VECTOR_MASK;
>>>> +
>>>> +             d = this_cpu_read(irq_map[vector]);
>>>> +             if (d)
>>>> +                     generic_handle_irq_desc(d);
>>>> +             else {
>>> See bracket rules.
>> Do you mean even if there is only one statement in the if condition,
>> we still need to do like this?
>> if (xxx) {
>>      yyy;
>> } else {
>>      zzz;
>> }
> Yes. It's documented.
>
>>>> +     msi_domain = pci_msi_create_irq_domain(pch_msi_handle[0],
>>>> +                                            &pch_msi_domain_info_v2, parent);
>>> Please don't do that. Convert this to use per device MSI domains.
>> OK, thanks. But it is better to split the conversion to another patch
>> (so we can convert both V1 and V2).
> Why adding it first?
>
> This can be done per interrupt chip. See the conversion series for
> ARM[64]:
>
>      https://lore.kernel.org/r/20240623142137.448898081@linutronix.de
>
> Thanks,
>
>          tglx

We consider that since the original extioi-msi is still using the 
legacy-MSI interrupt model at irq-loongson-pch-msi.c, if per-device-MSI 
is directly supported in the AVEC support patch, it will result in the 
simultaneous use of two MSI-interrupt-mode in irq-loongson-pch-msi.c, 
which may seem a bit strange. So we decided to split it into two 
patches, the first one using tlegace-MSI to support AVEC interrupt 
controllers, and the second one will be uniformly modified to use 
per-device-MSI

Tianyang