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Message-Id: <20240805023320.1287061-1-unicornxw@gmail.com>
Date: Mon, 5 Aug 2024 10:33:20 +0800
From: Chen Wang <unicornxw@...il.com>
To: paul.walmsley@...ive.com,
palmer@...belt.com,
aou@...s.berkeley.edu,
inochiama@...look.com,
conor.dooley@...rochip.com,
guoren@...nel.org,
emil.renner.berthing@...onical.com,
apatel@...tanamicro.com,
hal.feng@...rfivetech.com,
dfustini@...libre.com,
prabhakar.mahadev-lad.rj@...renesas.com,
linux-riscv@...ts.infradead.org,
linux-kernel@...r.kernel.org,
haijiao.liu@...hgo.com,
xiaoguang.xing@...hgo.com
Cc: Chen Wang <unicorn_wang@...look.com>
Subject: [PATCH] riscv: defconfig: sophgo: enable clks for sg2042
From: Chen Wang <unicorn_wang@...look.com>
Enable clk generators for sg2042 due to many peripherals rely on
these clocks.
Signed-off-by: Chen Wang <unicorn_wang@...look.com>
---
arch/riscv/configs/defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
index 0d678325444f..d43a028909e5 100644
--- a/arch/riscv/configs/defconfig
+++ b/arch/riscv/configs/defconfig
@@ -249,6 +249,9 @@ CONFIG_VIRTIO_BALLOON=y
CONFIG_VIRTIO_INPUT=y
CONFIG_VIRTIO_MMIO=y
CONFIG_CLK_SOPHGO_CV1800=y
+CONFIG_CLK_SOPHGO_SG2042_PLL=y
+CONFIG_CLK_SOPHGO_SG2042_CLKGEN=y
+CONFIG_CLK_SOPHGO_SG2042_RPGATE=y
CONFIG_SUN8I_DE2_CCU=m
CONFIG_RENESAS_OSTM=y
CONFIG_SUN50I_IOMMU=y
base-commit: de9c2c66ad8e787abec7c9d7eff4f8c3cdd28aed
--
2.34.1
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