linux-kernel - Re: [PATCH v4 3/3] riscv: dts: sophgo: Add SARADC description for Sophgo CV18XX

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Message-ID:
 <MA0P287MB28229B43DEFC2996023F8CDCFE862@MA0P287MB2822.INDP287.PROD.OUTLOOK.COM>
Date: Wed, 14 Aug 2024 07:32:22 +0800
From: Chen Wang <unicorn_wang@...look.com>
To: Inochi Amaoto <inochiama@...look.com>,
 Thomas Bonnefille <thomas.bonnefille@...tlin.com>,
 Jonathan Cameron <jic23@...nel.org>, Lars-Peter Clausen <lars@...afoo.de>,
 Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
 Conor Dooley <conor+dt@...nel.org>, Paul Walmsley
 <paul.walmsley@...ive.com>, Palmer Dabbelt <palmer@...belt.com>,
 Albert Ou <aou@...s.berkeley.edu>
Cc: Thomas Petazzoni <thomas.petazzoni@...tlin.com>,
 Miquèl Raynal <miquel.raynal@...tlin.com>,
 linux-iio@...r.kernel.org, devicetree@...r.kernel.org,
 linux-kernel@...r.kernel.org, linux-riscv@...ts.infradead.org
Subject: Re: [PATCH v4 3/3] riscv: dts: sophgo: Add SARADC description for
 Sophgo CV18XX


On 2024/8/13 9:50, Inochi Amaoto wrote:
> On Tue, Aug 13, 2024 at 09:45:53AM GMT, Chen Wang wrote:
>> On 2024/8/12 23:00, Thomas Bonnefille wrote:
>>> Adds SARADC nodes for the common Successive Approximation Analog to
>>> Digital Converter used in Sophgo CV18xx series SoC.
>>> This patch adds two nodes for the two controllers the board, one in
>>> the Active domain and the other in the No-Die domain.
>> Where is the node for the No-die domain?
> I have suggested Thomas not add the node for the RTC domain.
> It is not clear that which clock is used for the RTC domain,
> it will good to add this node after the RTC is implemented.
OK，so please update the commit message and mention this.
>
>>> Signed-off-by: Thomas Bonnefille <thomas.bonnefille@...tlin.com>
>>> ---
>>>    arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 20 ++++++++++++++++++++
>>>    1 file changed, 20 insertions(+)
>>>
>>> diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
>>> index 891932ae470f..71a2618852fa 100644
>>> --- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
>>> +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
>>> @@ -133,6 +133,26 @@ portd: gpio-controller@0 {
>>>    			};
>>>    		};
>>> +		saradc: adc@...0000 {
>>> +			compatible = "sophgo,cv1800b-saradc";
>>> +			reg = <0x030f0000 0x1000>;
>>> +			clocks = <&clk CLK_SARADC>;
>>> +			interrupts = <100 IRQ_TYPE_LEVEL_HIGH>;
>>> +			#address-cells = <1>;
>>> +			#size-cells = <0>;
>>> +			status = "disabled";
>>> +
>>> +			channel@0 {
>>> +				reg = <0>;
>>> +			};
>>> +			channel@1 {
>>> +				reg = <1>;
>>> +			};
>>> +			channel@2 {
>>> +				reg = <2>;
>>> +			};
>>> +		};
>>> +
>>>    		i2c0: i2c@...0000 {
>>>    			compatible = "snps,designware-i2c";
>>>    			reg = <0x04000000 0x10000>;
>>>