lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite for Android: free password hash cracker in your pocket
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <7f77dcc41173f2a20a0264b6242ecdac6ea85ad9.camel@samsung.com>
Date: Mon, 19 Aug 2024 18:32:27 +0900
From: Kwanghoon Son <k.son@...sung.com>
To: Sunyeal Hong <sunyeal.hong@...sung.com>, Krzysztof Kozlowski
	<krzk@...nel.org>, Sylwester Nawrocki <s.nawrocki@...sung.com>, Chanwoo Choi
	<cw00.choi@...sung.com>, Alim Akhtar <alim.akhtar@...sung.com>, Michael
	Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>, Rob
	Herring <robh@...nel.org>,  Conor Dooley <conor+dt@...nel.org>
Cc: linux-samsung-soc@...r.kernel.org, linux-clk@...r.kernel.org,
	devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org, 
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH v6 4/4] clk: samsung: add top clock support for
 ExynosAuto v920 SoC

On Mon, 2024-08-19 at 14:24 +0900, Sunyeal Hong wrote:
> This adds support for CMU_TOP which generates clocks for all the
> function blocks such as CORE, HSI0/1/2, PERIC0/1 and so on. For
> CMU_TOP, PLL_SHARED0,1,2,3,4 and 5 will be the sources of this block
> and they will generate bus clocks.
> 
> Signed-off-by: Sunyeal Hong <sunyeal.hong@...sung.com>
> ---
>  drivers/clk/samsung/Makefile             |    1 +
>  drivers/clk/samsung/clk-exynosautov920.c | 1173 ++++++++++++++++++++++
>  2 files changed, 1174 insertions(+)
>  create mode 100644 drivers/clk/samsung/clk-exynosautov920.c
> 
> diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
> index 3056944a5a54..f1ba48758c78 100644
> --- a/drivers/clk/samsung/Makefile
> +++ b/drivers/clk/samsung/Makefile
> @@ -21,6 +21,7 @@ obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK)	+= clk-exynos7.o
>  obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK)	+= clk-exynos7885.o
>  obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK)	+= clk-exynos850.o
>  obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK)	+= clk-exynosautov9.o
> +obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK)	+= clk-exynosautov920.o
>  obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK)	+= clk-gs101.o
>  obj-$(CONFIG_S3C64XX_COMMON_CLK)	+= clk-s3c64xx.o
>  obj-$(CONFIG_S5PV210_COMMON_CLK)	+= clk-s5pv210.o clk-s5pv210-audss.o
> diff --git a/drivers/clk/samsung/clk-exynosautov920.c b/drivers/clk/samsung/clk-exynosautov920.c
> new file mode 100644
> index 000000000000..c17d25e3c9a0
> --- /dev/null
> +++ b/drivers/clk/samsung/clk-exynosautov920.c

[snip]

> +};
> +
> +static const struct samsung_cmu_info peric0_cmu_info __initconst = {
> +	.mux_clks		= peric0_mux_clks,
> +	.nr_mux_clks		= ARRAY_SIZE(peric0_mux_clks),
> +	.div_clks		= peric0_div_clks,
> +	.nr_div_clks		= ARRAY_SIZE(peric0_div_clks),
> +	.nr_clk_ids		= CLKS_NR_PERIC0,
> +	.clk_regs		= peric0_clk_regs,
> +	.nr_clk_regs		= ARRAY_SIZE(peric0_clk_regs),
> +	.clk_name		= "dout_clkcmu_peric0_noc",

same question.
Isn't it "noc"?
https://lore.kernel.org/linux-samsung-soc/58dfae564a4a624e464c7803a309f1f07b5ae83d.camel@samsung.com/

In my case(autov9), if put wrong clk_name dmesg will show that,
exynos_arm64_register_cmu: could not enable bus clock ...; err = -2

Kwang.




Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ