linux-kernel - Re: [PATCH v2 1/4] dt-bindings: clock: qcom: Add CMN PLL clock controller for IPQ SoC

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Message-ID: <krbpzjccn6xvnpfsa7eeeowmtjuuw4yp72qqqbeq2icxrqvdo4@x6pawrcctyd3>
Date: Wed, 21 Aug 2024 10:33:19 +0200
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Luo Jie <quic_luoj@...cinc.com>
Cc: Bjorn Andersson <andersson@...nel.org>, 
	Michael Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>, Rob Herring <robh@...nel.org>, 
	Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, 
	Catalin Marinas <catalin.marinas@....com>, Will Deacon <will@...nel.org>, 
	Konrad Dybcio <konradybcio@...nel.org>, linux-arm-msm@...r.kernel.org, linux-clk@...r.kernel.org, 
	devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, 
	linux-arm-kernel@...ts.infradead.org, quic_kkumarcs@...cinc.com, quic_suruchia@...cinc.com, 
	quic_pavir@...cinc.com, quic_linchen@...cinc.com, quic_leiwei@...cinc.com, 
	bartosz.golaszewski@...aro.org, srinivas.kandagatla@...aro.org
Subject: Re: [PATCH v2 1/4] dt-bindings: clock: qcom: Add CMN PLL clock
 controller for IPQ SoC

On Tue, Aug 20, 2024 at 10:02:42PM +0800, Luo Jie wrote:
> The CMN PLL controller provides clocks to networking hardware blocks
> on Qualcomm IPQ9574 SoC. It receives input clock from the on-chip Wi-Fi,
> and produces output clocks at fixed rates. These output rates are
> predetermined, and are unrelated to the input clock rate. The output
> clocks are supplied to the Ethernet hardware such as PPE (packet
> process engine) and the externally connected switch or PHY device.
> 
> Signed-off-by: Luo Jie <quic_luoj@...cinc.com>
> ---
>  .../bindings/clock/qcom,ipq9574-cmn-pll.yaml       | 70 ++++++++++++++++++++++
>  include/dt-bindings/clock/qcom,ipq-cmn-pll.h       | 15 +++++
>  2 files changed, 85 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
> new file mode 100644
> index 000000000000..7ad04b58a698
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
> @@ -0,0 +1,70 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/qcom,ipq9574-cmn-pll.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm CMN PLL Clock Controller on IPQ SoC
> +
> +maintainers:
> +  - Bjorn Andersson <andersson@...nel.org>
> +  - Luo Jie <quic_luoj@...cinc.com>
> +
> +description:
> +  The CMN PLL clock controller expects a reference input clock.

You did not explain what is CMN. Is this some sort of acronym?

Best regards,
Krzysztof